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authorMarek Olšák <[email protected]>2015-03-02 02:40:57 +0100
committerMarek Olšák <[email protected]>2015-03-16 12:54:18 +0100
commitf9fd0c4a55afd97fd34d0e846000c75f5f6ecac2 (patch)
tree3174aea77bb359607379b6f8431c62cd42daee08
parentd73c1c1304a205c8bf6d1cad1dd1d9a421ce2f32 (diff)
radeonsi: add support for SQRT
Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
-rw-r--r--src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c2
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 80267233959..385d3ada9d0 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1363,6 +1363,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
+ bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 87eeac6fbe8..993b153d1f4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -403,7 +403,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
- return 0;
+ return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* Indirection of geometry shader input dimension is not
* handled yet