diff options
| author | Dave Airlie <[email protected]> | 2017-08-15 15:18:04 +1000 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2017-08-19 01:36:25 +0100 |
| commit | f70f21656454a50c25b17add5e20e6199aad2b8b (patch) | |
| tree | a40c6cedc907866b0f04e8dd11202ba4e65ea8e4 | |
| parent | 827bf790521b584b54b27be4a67a189c39ed76b0 (diff) | |
radv/gfx9: remove some leftover gfx6 descriptor setup.
We set this later in the non-gfx9 path, just remove these
bits from here.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Cc: "17.2" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit fc600eb98d5846fe59f4a79ed1c7ad2a0667e927)
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ce1ee24036e..a7ed7cc86e9 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -205,7 +205,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, { uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0; uint64_t va = gpu_address; - unsigned pitch = base_level_info->nblk_x * block_width; enum chip_class chip_class = device->physical_device->rad_info.chip_class; uint64_t meta_va = 0; if (chip_class >= GFX9) { @@ -221,9 +220,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, state[0] |= image->surface.u.legacy.tile_swizzle; state[1] &= C_008F14_BASE_ADDRESS_HI; state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); - state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level, - is_stencil)); - state[4] |= S_008F20_PITCH_GFX6(pitch - 1); if (chip_class >= VI) { state[6] &= C_008F28_COMPRESSION_EN; |