diff options
| author | Dave Airlie <[email protected]> | 2011-11-04 17:12:02 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2011-11-04 17:17:17 +0000 |
| commit | 71f1d468b4e183c45e4f76f7951beb44dd74a707 (patch) | |
| tree | 8bdd9394a6e43061f9d0ba244b1e6774761cb625 | |
| parent | 2431c992cb97235c6e500bd1c0c267e608b99052 (diff) | |
radeon/r200: fix r100/r200 blit to use the offsets.
This is needed to do proper renderbuffer operation on mipmaps.
Signed-off-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_blit.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_blit.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c index 05a15c444cc..487bb5b78e1 100644 --- a/src/mesa/drivers/dri/r200/r200_blit.c +++ b/src/mesa/drivers/dri/r200/r200_blit.c @@ -278,7 +278,7 @@ static void inline emit_tx_setup(struct r200_context *r200, OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32); OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); - OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); } @@ -332,7 +332,7 @@ static inline void emit_cb_setup(struct r200_context *r200, OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); - OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c index fe14540bc2e..25d21197562 100644 --- a/src/mesa/drivers/dri/radeon/radeon_blit.c +++ b/src/mesa/drivers/dri/radeon/radeon_blit.c @@ -156,7 +156,7 @@ static void inline emit_tx_setup(struct r100_context *r100, OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32); OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1); - OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); } @@ -206,7 +206,7 @@ static inline void emit_cb_setup(struct r100_context *r100, OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); - OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); |