diff options
| author | Kenneth Graunke <[email protected]> | 2013-12-11 15:22:26 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-01-20 15:38:23 -0800 |
| commit | 4b9e5c985c2d25c848c2c1e0d1ac1ef1124d8480 (patch) | |
| tree | 78cb6b06ce2368fb8f099af80b10f2b16278e676 | |
| parent | 9420b577ddeefe04c9812e9b62628e2f01be06cf (diff) | |
i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.
The PIPE_CONTROL packet actually has 5 DWords on Gen6+:
1. Header
2. Flags
3. Address
4. Immediate Data: Lower DWord
5. Immediate Data: Upper DWord
We just never emitted the last one. While it appears to work, it's
probably safer to emit the entire thing.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 041b18dd34b..12c7eccae69 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -441,11 +441,12 @@ void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) { if (brw->gen >= 6) { - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); OUT_BATCH(flags); OUT_BATCH(0); OUT_BATCH(0); + OUT_BATCH(0); ADVANCE_BATCH(); } else { BEGIN_BATCH(4); |