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authorChad Versace <[email protected]>2019-08-01 16:25:47 -0700
committerChad Versace <[email protected]>2019-08-01 16:36:00 -0700
commit178d22da4903aed2a560e6c9a55eea39cab58508 (patch)
tree9504947f502d04dc50c302d8f46ecb7919732015
parent5d29487a443e551850e48c331254955e74bea7f9 (diff)
WIP: anv: Fix assumptions broken by
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
-rw-r--r--src/intel/vulkan/anv_image.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 27ecbaf673f..d2537675374 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1095,7 +1095,7 @@ anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
return ISL_AUX_USAGE_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
- assert(image->tiling.vk == VK_IMAGE_TILING_OPTIMAL);
+ assert(!anv_tiling_is_linear(image->tiling));
/* Stencil has no aux */
assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -1225,7 +1225,7 @@ anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
return ANV_FAST_CLEAR_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
- assert(image->tiling.vk == VK_IMAGE_TILING_OPTIMAL);
+ assert(!anv_tiling_is_linear(image->tiling));
/* Stencil has no aux */
assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);