diff options
| author | Rob Clark <[email protected]> | 2019-05-30 09:04:57 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-05-31 12:58:33 -0700 |
| commit | f9fa456e1d09f1a6b2dccde056b3754f3f198ba7 (patch) | |
| tree | 7b315f2cecb722e56a64ab5f88ecc7d9b3b32247 | |
| parent | 5d43b806ba3a2026d11e20ec655a9ead116c88ef (diff) | |
freedreno/ir3: set more barrier bits
Blob is also setting the .l bit, and it seems to solve some intermittent
failures with a couple of deqp's:
dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i
dEQP-GLES31.functional.image_load_store.2d.qualifiers.volatile_r32f
Signed-off-by: Rob Clark <[email protected]>
Acked-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 6851f311d5a..be141ce4e4a 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1048,6 +1048,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr) barrier->cat7.g = true; barrier->cat7.r = true; barrier->cat7.w = true; + barrier->cat7.l = true; barrier->barrier_class = IR3_BARRIER_IMAGE_W | IR3_BARRIER_BUFFER_W; barrier->barrier_conflict = |