diff options
| author | Kenneth Graunke <[email protected]> | 2013-12-11 21:53:27 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-01-06 15:45:42 -0800 |
| commit | f6b10544cda34ec2e7f43de217e28ab2bdc2f63d (patch) | |
| tree | 4b7b4abac9eb1a1f3ba026361c7c34ccafe1b584 | |
| parent | f8432832a7f3d3cc01f8bab8358069029d575ef0 (diff) | |
i965: Remove unused PIPE_CONTROL defines.
Both brw_defines.h and intel_reg.h defined PIPE_CONTROL fields, which
had similar names, but couldn't be used in the same way. (One had
built-in shifts, and the other didn't...)
Delete the unused set to preserve sanity.
(Eric wrote an almost identical patch back in August, so I believe he
approves.)
Signed-off-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index dc38acea21b..0fc24a7ede9 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -38,14 +38,6 @@ /* 3D state: */ -#define PIPE_CONTROL_NOWRITE 0x00 -#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 -#define PIPE_CONTROL_WRITEDEPTH 0x02 -#define PIPE_CONTROL_WRITETIMESTAMP 0x03 - -#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 -#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 - #define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */ /* DW0 */ # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10 @@ -1919,8 +1911,6 @@ enum brw_wm_barycentric_interp_mode { /* DW2: start address */ /* DW3: end address. */ -#define CMD_PIPE_CONTROL 0x7a00 - #define CMD_MI_FLUSH 0x0200 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2)) |