diff options
| author | Lionel Landwerlin <[email protected]> | 2019-04-18 11:57:57 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2019-04-18 17:43:08 +0100 |
| commit | d1be67db39463b48369cb71979ed18662b2c157e (patch) | |
| tree | afe1c0ea5984da12c625bf5e75b57746de5b8cea | |
| parent | c2b8fb9a810003791bfa65b3173ccc28bfe14484 (diff) | |
iris: implement WaEnableStateCacheRedirectToCS
This 3d performance workaround was initially put in the kernel but the
media driver requires different settings so the register has been
whitelisted in i915 [1] and userspace drivers are left initializing it as
they wish.
[1] : https://patchwork.freedesktop.org/series/59494/
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 7 | ||||
| -rw-r--r-- | src/intel/genxml/gen11.xml | 5 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 8d5383598d2..2c85ba3778a 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -721,6 +721,13 @@ iris_init_render_context(struct iris_screen *screen, } iris_emit_lri(batch, COMMON_SLICE_CHICKEN3, reg_val); + iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1), ®_val, reg) { + reg.StateCacheRedirectToCSSectionEnable = true; + reg.StateCacheRedirectToCSSectionEnableMask = true; + } + iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val); + + // XXX: 3D_MODE? #endif diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 83e03f6f7f0..243752abafc 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -7015,6 +7015,11 @@ <field name="SFBE Done" start="25" end="25" type="bool"/> </register> + <register name="SLICE_COMMON_ECO_CHICKEN1" length="1" num="0x731c"> + <field name="State Cache Redirect To CS Section Enable" start="11" end="11" type="bool"/> + <field name="State Cache Redirect To CS Section Enable Mask" start="27" end="27" type="bool"/> + </register> + <register name="SO_NUM_PRIMS_WRITTEN0" length="2" num="0x5200"> <field name="Num Prims Written Count" start="0" end="63" type="uint"/> </register> |