diff options
| author | Samuel Pitoiset <[email protected]> | 2020-04-08 09:30:47 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-21 15:06:48 +0000 |
| commit | b3c87c52ea4b8f311f0e87c76420e94b7149d8b0 (patch) | |
| tree | 08b4a4238ba8fa633957e7962ac4ce64fefcb0d4 | |
| parent | dfa62d97a0fdfd320f8d08e44883342c186acaae (diff) | |
aco: implement 8-bit/16-bit nir_intrinsic_quad_*
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Rhys Perry <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 98f10074645..d9a5742164c 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -7753,6 +7753,14 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp, bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)))); emit_wqm(ctx, tmp, dst); + } else if (instr->dest.ssa.bit_size == 8) { + Temp tmp = bld.tmp(v1); + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v3b), tmp); + } else if (instr->dest.ssa.bit_size == 16) { + Temp tmp = bld.tmp(v1); + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp); } else if (instr->dest.ssa.bit_size == 32) { if (ctx->program->chip_class >= GFX8) emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst); @@ -7817,6 +7825,14 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl); Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src); emit_wqm(ctx, tmp, dst); + } else if (instr->dest.ssa.bit_size == 8) { + Temp tmp = bld.tmp(v1); + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v3b), tmp); + } else if (instr->dest.ssa.bit_size == 16) { + Temp tmp = bld.tmp(v1); + emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); + bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp); } else if (instr->dest.ssa.bit_size == 32) { Temp tmp; if (ctx->program->chip_class >= GFX8) |