diff options
| author | Marek Olšák <[email protected]> | 2019-12-09 19:27:26 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-12-10 16:32:37 -0500 |
| commit | a305543c8dbfff4e6bdd85f2643e95c414654cfd (patch) | |
| tree | cc6a41983b02532d3589f1ad1df154f4467fdbde | |
| parent | aced18aa61232193fb90b9e08d90a1e54721a8bf (diff) | |
radeonsi: don't rely on CLEAR_STATE to set PA_SC_GENERIC_SCISSOR_*
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 26518244c54..ac3d14d8f66 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5460,15 +5460,17 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1)); + /* CLEAR_STATE doesn't restore these correctly. */ + si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); + si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, + S_028244_BR_X(16384) | S_028244_BR_Y(16384)); + /* CLEAR_STATE doesn't clear these correctly on certain generations. * I don't know why. Deduced by trial and error. */ if (sctx->chip_class <= GFX7 || !has_clear_state) { si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); - si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); - si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, - S_028244_BR_X(16384) | S_028244_BR_Y(16384)); si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); |