diff options
| author | Jonathan Marek <[email protected]> | 2019-11-18 16:17:55 -0500 |
|---|---|---|
| committer | Jonathan Marek <[email protected]> | 2019-11-21 22:21:57 +0000 |
| commit | 91fd83d1420c8e9f94b08356ab48f9ab15329645 (patch) | |
| tree | 2d8a4e65f9baa17c3aeba0663fa44733da5a91c8 | |
| parent | 6613a4a0295879dc3ba2c13198f3ad5de7919487 (diff) | |
freedreno/regs: update UBWC related bits
Signed-off-by: Jonathan Marek <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/freedreno/registers/a6xx.xml | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_image.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_texture.c | 2 |
3 files changed, 11 insertions, 7 deletions
diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index 3f482edca4a..fe5b6adc37b 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -3294,7 +3294,12 @@ to upconvert to 32b float internally? --> <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> - <bitfield name="UNK27" pos="27" type="boolean"/> + <!-- + by default levels with w < 16 are linear + TILE_ALL makes all levels have tiling + seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) + --> + <bitfield name="TILE_ALL" pos="27" type="boolean"/> <bitfield name="FLAG" pos="28" type="boolean"/> </reg32> <reg32 offset="4" name="4"> @@ -3315,11 +3320,10 @@ to upconvert to 32b float internally? <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> </reg32> <reg32 offset="10" name="10"> - <!-- - I see some other bits set by blob above FLAG_BUFFER_PITCH, but they - don't seem to be particularly sensible... or needed for UBWC to work - --> <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> + <!-- log2 size of the first level, required for mipmapping --> + <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> + <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> </reg32> <reg32 offset="11" name="11"/> <reg32 offset="12" name="12"/> diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c index 3b476440856..b6d38379945 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c @@ -183,7 +183,7 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img) A6XX_TEX_CONST_2_TYPE(img->type) | A6XX_TEX_CONST_2_PITCH(img->pitch)); OUT_RING(ring, A6XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch) | - COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27)); + COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL)); if (img->bo) { OUT_RELOC(ring, img->bo, img->offset, (uint64_t)A6XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c index 5df197c62c9..6ef7b16ab87 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c @@ -318,7 +318,7 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, } if (so->ubwc_enabled) { - so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27; + so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL; } return &so->base; |