diff options
| author | Wladimir J. van der Laan <[email protected]> | 2017-10-01 11:21:19 +0200 |
|---|---|---|
| committer | Christian Gmeiner <[email protected]> | 2017-10-03 19:49:38 +0200 |
| commit | 80f608b5304396fdfc16cd318f332d93f188c381 (patch) | |
| tree | 157770e698429eaad78d2d5f3b3c3a3dc4a3a277 | |
| parent | df82012b2cbac47694a490738c5e6a33e3a69ee3 (diff) | |
etnaviv: Support opcodes with bit 6 set in assembler
Support opcodes with bit 6 set in assembler, and assert that only ops
0x00..0x7f are used.
Signed-off-by: Wladimir J. van der Laan <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
| -rw-r--r-- | src/gallium/drivers/etnaviv/etnaviv_asm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/etnaviv/etnaviv_asm.c b/src/gallium/drivers/etnaviv/etnaviv_asm.c index 7d6270ca1f9..8ef4dc9f719 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_asm.c +++ b/src/gallium/drivers/etnaviv/etnaviv_asm.c @@ -68,7 +68,9 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst) if (!check_uniforms(inst)) BUG("error: generating instruction that accesses two different uniforms"); - out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode) | + assert(!(inst->opcode&~0x7f)); + + out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode & 0x3f) | VIV_ISA_WORD_0_COND(inst->cond) | COND(inst->sat, VIV_ISA_WORD_0_SAT) | COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) | @@ -88,6 +90,7 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst) VIV_ISA_WORD_2_SRC0_RGROUP(inst->src[0].rgroup) | COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) | VIV_ISA_WORD_2_SRC1_REG(inst->src[1].reg) | + COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) | VIV_ISA_WORD_2_SRC1_SWIZ(inst->src[1].swiz) | COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) | COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) | |