diff options
| author | Jordan Justen <[email protected]> | 2015-02-20 12:12:25 -0800 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2015-02-21 11:40:53 -0800 |
| commit | 49a938a265f5959c9b558995cc658f80acb6eb18 (patch) | |
| tree | deca213db3b88b9ceb7300e3351adce5d07b3d1d | |
| parent | 17fbd854e03a569d71885e54a98dab45bfa6b897 (diff) | |
i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data
The brw_imm_ud will yield a HW_REG which then will introduce a barrier
for certain optimization opportunities.
No piglit regressions seen with gen8 (simd8vs).
Suggested-by: Matt Turner <[email protected]>
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index fa7d32cdab2..b1b75821c73 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3016,7 +3016,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xffff)))->force_writemask_all = true; + fs_reg(0xffff)))->force_writemask_all = true; } length++; @@ -3079,7 +3079,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xffff)))->force_writemask_all = true; + fs_reg(0xffff)))->force_writemask_all = true; } /* Set the surface read offset. */ |