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authorEric Anholt <[email protected]>2019-04-22 10:40:47 -0700
committerEric Anholt <[email protected]>2019-04-26 12:42:30 -0700
commit4358904c06838138b17e7e81b55d3a04d50dde1e (patch)
treee16203242c30c0e0ded1c96d5c0b81d81afbb08e
parentc74d0e7f6278b885b6b195b8e8daef36c775d4ec (diff)
v3d: Add a note about i/o indirection for future performance work.
-rw-r--r--src/broadcom/compiler/nir_to_vir.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c
index 30fd4002ef9..3fa2e1de953 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1737,6 +1737,9 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
break;
case nir_intrinsic_load_input:
+ /* Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
+ * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
+ */
offset = (nir_intrinsic_base(instr) +
nir_src_as_uint(instr->src[0]));
if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
@@ -1778,6 +1781,10 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
break;
case nir_intrinsic_store_output:
+ /* XXX perf: Use stvpmv with uniform non-constant offsets and
+ * stvpmd with non-uniform offsets and enable
+ * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
+ */
if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
offset = ((nir_intrinsic_base(instr) +
nir_src_as_uint(instr->src[1])) * 4 +