diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:44:08 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:56 -0400 |
| commit | 3060f62340b2f232907db0c48b6c6c6eba3d1752 (patch) | |
| tree | 8a7937afbe0531b11309e7893934898e98e5cdb2 | |
| parent | 09f1bab483cc8011a6299e2aca805b6ad06aab82 (diff) | |
ac/gpu_info: add has_bo_metadata
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 3 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 |
4 files changed, 5 insertions, 2 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 6f2fea895be..68750b2db28 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -319,6 +319,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->kernel_flushes_hdp_before_ib = true; info->htile_cmask_support_1d_tiling = true; info->si_TA_CS_BC_BASE_ADDR_allowed = true; + info->has_bo_metadata = true; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -469,6 +470,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib); printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling); printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); + printf(" has_bo_metadata = %u\n", info->has_bo_metadata); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index bc6350b5625..340c368bda3 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -99,6 +99,7 @@ struct radeon_info { bool kernel_flushes_hdp_before_ib; bool htile_cmask_support_1d_tiling; bool si_TA_CS_BC_BASE_ADDR_allowed; + bool has_bo_metadata; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 144516e3a5e..d2814c4f300 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -608,8 +608,7 @@ static void si_query_opaque_metadata(struct si_screen *sscreen, uint32_t desc[8], i; bool is_array = util_texture_is_array(res->target); - /* DRM 2.x.x doesn't support this. */ - if (sscreen->info.drm_major != 3) + if (!sscreen->info.has_bo_metadata) return; assert(rtex->dcc_separate_buffer == NULL); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 6040134c2da..d7ecfe9f240 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -533,6 +533,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK || ws->info.drm_minor >= 38; ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; + ws->info.has_bo_metadata = false; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |