diff options
author | Timur Kristóf <[email protected]> | 2019-12-31 13:39:56 +0100 |
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committer | Timur Kristóf <[email protected]> | 2019-12-31 14:22:31 +0100 |
commit | 11e62a9734c631fa38f1e7b415f5b98f6a28589f (patch) | |
tree | 3e159d42ed4b2bc33a8ec7228ac1452365edba33 | |
parent | 182679e7c5523bea54f51b82bae74c8d42ef4c94 (diff) |
aco: Fix uniform i2i64.
Fixes 240 failing test cases in dEQP-VK.spirv_assembly which
were failing due to a bad s_ashr_i32 instruction. This commit
fixes the instruction format along with the definitions of the
instruction.
Fixes: 11f43caaeca166c96ae49dbd506b6f58dd4a13fb
Cc: 19.3 <[email protected]>
Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
-rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index c498882252a..bf8da815750 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2099,7 +2099,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) case nir_op_i2i64: { Temp src = get_alu_src(ctx, instr->src[0]); if (src.regClass() == s1) { - Temp high = bld.sopc(aco_opcode::s_ashr_i32, bld.def(s1, scc), src, Operand(31u)); + Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u)); bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high); } else if (src.regClass() == v1) { Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src); |