diff options
author | Dave Airlie <[email protected]> | 2017-05-02 09:49:14 +1000 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2017-05-03 06:00:17 +1000 |
commit | 7e8d0a402b0a0db431da04f5126853de50729ed7 (patch) | |
tree | 74d4764a218de4eb1e16ee4a0bd111e2b66cbe70 | |
parent | d5400a5ec2afdbca1c2745183f171ac72d6f0647 (diff) |
radv: move some image info into a separate struct.
This is to rework the surface code like radeonsi.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_device.c | 14 | ||||
-rw-r--r-- | src/amd/vulkan/radv_image.c | 63 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_blit.c | 6 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_bufimage.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 17 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_copy.c | 8 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_decompress.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 10 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve.c | 18 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve_cs.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_private.h | 13 | ||||
-rw-r--r-- | src/amd/vulkan/radv_radeon_winsys.h | 9 |
13 files changed, 90 insertions, 80 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index de103855158..198c599fe0a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3030,8 +3030,8 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL && (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) && cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 && - cmd_buffer->state.render_area.extent.width == image->extent.width && - cmd_buffer->state.render_area.extent.height == image->extent.height) { + cmd_buffer->state.render_area.extent.width == image->info.width && + cmd_buffer->state.render_area.extent.height == image->info.height) { /* The clear will initialize htile. */ return; } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED && diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index dd401f4b0be..1301801ef47 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2640,8 +2640,8 @@ radv_initialise_color_surface(struct radv_device *device, cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) | S_028C74_TILE_MODE_INDEX(tile_mode_index); - if (iview->image->samples > 1) { - unsigned log_samples = util_logbase2(iview->image->samples); + if (iview->image->info.samples > 1) { + unsigned log_samples = util_logbase2(iview->image->info.samples); cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_samples); @@ -2705,7 +2705,7 @@ radv_initialise_color_surface(struct radv_device *device, format != V_028C70_COLOR_24_8) | S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian); - if (iview->image->samples > 1) + if (iview->image->info.samples > 1) if (iview->image->fmask.size) cb->cb_color_info |= S_028C70_COMPRESSION(1); @@ -2718,7 +2718,7 @@ radv_initialise_color_surface(struct radv_device *device, if (device->physical_device->rad_info.chip_class >= VI) { unsigned max_uncompressed_block_size = 2; - if (iview->image->samples > 1) { + if (iview->image->info.samples > 1) { if (iview->image->surface.bpe == 1) max_uncompressed_block_size = 0; else if (iview->image->surface.bpe == 2) @@ -2786,8 +2786,8 @@ radv_initialise_ds_surface(struct radv_device *device, ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1); - if (iview->image->samples > 1) - ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples)); + if (iview->image->info.samples > 1) + ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples)); if (iview->image->surface.flags & RADEON_SURF_SBUFFER) ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8); @@ -2838,7 +2838,7 @@ radv_initialise_ds_surface(struct radv_device *device, * Check piglit's arb_texture_multisample-stencil-clear * test if you want to try changing this. */ - if (iview->image->samples <= 1) + if (iview->image->info.samples <= 1) ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1); } else /* Use all of the htile_buffer for depth if there's no stencil. */ diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 3586e4c158b..cd278edf224 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -291,17 +291,17 @@ si_make_texture_descriptor(struct radv_device *device, data_format = 0; } - type = radv_tex_dim(image->type, view_type, image->array_size, image->samples, + type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)); if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { height = 1; - depth = image->array_size; + depth = image->info.array_size; } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) { if (view_type != VK_IMAGE_VIEW_TYPE_3D) - depth = image->array_size; + depth = image->info.array_size; } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE) - depth = image->array_size / 6; + depth = image->info.array_size / 6; state[0] = 0; state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) | @@ -312,12 +312,12 @@ si_make_texture_descriptor(struct radv_device *device, S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) | S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) | - S_008F1C_BASE_LEVEL(image->samples > 1 ? + S_008F1C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) | - S_008F1C_LAST_LEVEL(image->samples > 1 ? - util_logbase2(image->samples) : + S_008F1C_LAST_LEVEL(image->info.samples > 1 ? + util_logbase2(image->info.samples) : last_level) | - S_008F1C_POW2_PAD(image->levels > 1) | + S_008F1C_POW2_PAD(image->info.levels > 1) | S_008F1C_TYPE(type)); state[4] = S_008F20_DEPTH(depth - 1); state[5] = (S_008F24_BASE_ARRAY(first_layer) | @@ -333,7 +333,7 @@ si_make_texture_descriptor(struct radv_device *device, /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. */ - if (device->physical_device->rad_info.chip_class <= CIK && image->samples <= 1) { + if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) { if (first_level == last_level) state[7] = C_008F30_MAX_ANISO_RATIO; else @@ -349,7 +349,7 @@ si_make_texture_descriptor(struct radv_device *device, va = gpu_address + image->offset + image->fmask.offset; - switch (image->samples) { + switch (image->info.samples) { case 2: fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; break; @@ -410,10 +410,10 @@ radv_query_opaque_metadata(struct radv_device *device, si_make_texture_descriptor(device, image, true, (VkImageViewType)image->type, image->vk_format, - &fixedmapping, 0, image->levels - 1, 0, - image->array_size, - image->extent.width, image->extent.height, - image->extent.depth, + &fixedmapping, 0, image->info.levels - 1, 0, + image->info.array_size, + image->info.width, image->info.height, + image->info.depth, desc, NULL); si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0], 0, 0, @@ -428,10 +428,10 @@ radv_query_opaque_metadata(struct radv_device *device, memcpy(&md->metadata[2], desc, sizeof(desc)); /* Dwords [10:..] contain the mipmap level offsets. */ - for (i = 0; i <= image->levels - 1; i++) + for (i = 0; i <= image->info.levels - 1; i++) md->metadata[10+i] = image->surface.level[i].offset >> 8; - md->size_metadata = (11 + image->levels - 1) * 4; + md->size_metadata = (11 + image->info.levels - 1) * 4; } void @@ -513,7 +513,7 @@ static void radv_image_alloc_fmask(struct radv_device *device, struct radv_image *image) { - radv_image_get_fmask_info(device, image, image->samples, &image->fmask); + radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask); image->fmask.offset = align64(image->size, image->fmask.alignment); image->size = image->fmask.offset + image->fmask.size; @@ -565,7 +565,7 @@ radv_image_get_cmask_info(struct radv_device *device, out->slice_tile_max -= 1; out->alignment = MAX2(256, base_align); - out->size = (image->type == VK_IMAGE_TYPE_3D ? image->extent.depth : image->array_size) * + out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) * align(slice_bytes, base_align); } @@ -597,7 +597,7 @@ static void radv_image_alloc_htile(struct radv_device *device, struct radv_image *image) { - if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->levels > 1) { + if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) { image->surface.htile_size = 0; return; } @@ -636,11 +636,14 @@ radv_image_create(VkDevice _device, memset(image, 0, sizeof(*image)); image->type = pCreateInfo->imageType; - image->extent = pCreateInfo->extent; + image->info.width = pCreateInfo->extent.width; + image->info.height = pCreateInfo->extent.height; + image->info.depth = pCreateInfo->extent.depth; + image->info.samples = pCreateInfo->samples; + image->info.array_size = pCreateInfo->arrayLayers; + image->info.levels = pCreateInfo->mipLevels; + image->vk_format = pCreateInfo->format; - image->levels = pCreateInfo->mipLevels; - image->array_size = pCreateInfo->arrayLayers; - image->samples = pCreateInfo->samples; image->tiling = pCreateInfo->tiling; image->usage = pCreateInfo->usage; image->flags = pCreateInfo->flags; @@ -669,9 +672,9 @@ radv_image_create(VkDevice _device, if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) && pCreateInfo->mipLevels == 1 && - !image->surface.dcc_size && image->extent.depth == 1 && can_cmask_dcc) + !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc) radv_image_alloc_cmask(device, image); - if (image->samples > 1 && vk_format_is_color(pCreateInfo->format)) { + if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) { radv_image_alloc_fmask(device, image); } else if (vk_format_is_depth(pCreateInfo->format)) { @@ -717,11 +720,11 @@ radv_image_view_init(struct radv_image_view *iview, switch (image->type) { case VK_IMAGE_TYPE_1D: case VK_IMAGE_TYPE_2D: - assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->array_size); + assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size); break; case VK_IMAGE_TYPE_3D: assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 - <= radv_minify(image->extent.depth, range->baseMipLevel)); + <= radv_minify(image->info.depth, range->baseMipLevel)); break; default: unreachable("bad VkImageType"); @@ -740,9 +743,9 @@ radv_image_view_init(struct radv_image_view *iview, } iview->extent = (VkExtent3D) { - .width = radv_minify(image->extent.width , range->baseMipLevel), - .height = radv_minify(image->extent.height, range->baseMipLevel), - .depth = radv_minify(image->extent.depth , range->baseMipLevel), + .width = radv_minify(image->info.width , range->baseMipLevel), + .height = radv_minify(image->info.height, range->baseMipLevel), + .depth = radv_minify(image->info.depth , range->baseMipLevel), }; iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format), diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c index cc8ca328cd2..92a1f9dbb92 100644 --- a/src/amd/vulkan/radv_meta_blit.c +++ b/src/amd/vulkan/radv_meta_blit.c @@ -240,7 +240,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, float tex_coord[3]; } vb_data[3]; - assert(src_image->samples == dest_image->samples); + assert(src_image->info.samples == dest_image->info.samples); unsigned vb_size = 3 * sizeof(*vb_data); vb_data[0] = (struct blit_vb_data) { .tex_coord = { @@ -495,8 +495,8 @@ void radv_CmdBlitImage( * vkCmdBlitImage must not be used for multisampled source or * destination images. Use vkCmdResolveImage for this purpose. */ - assert(src_image->samples == 1); - assert(dest_image->samples == 1); + assert(src_image->info.samples == 1); + assert(dest_image->info.samples == 1); radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer); diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 09a29d2d0cf..1d491ac05a5 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -1213,5 +1213,5 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); - radv_unaligned_dispatch(cmd_buffer, dst->image->extent.width, dst->image->extent.height, 1); + radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1); } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index d72f4c858da..190af651a1a 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -371,7 +371,7 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const uint32_t subpass_att = clear_att->colorAttachment; const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment; const struct radv_image_view *iview = fb->attachments[pass_att].attachment; - const uint32_t samples = iview->image->samples; + const uint32_t samples = iview->image->info.samples; const uint32_t samples_log2 = ffs(samples) - 1; unsigned fs_key = radv_format_meta_fs_key(iview->vk_format); struct radv_pipeline *pipeline; @@ -661,7 +661,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; VkImageAspectFlags aspects = clear_att->aspectMask; const struct radv_image_view *iview = fb->attachments[pass_att].attachment; - const uint32_t samples = iview->image->samples; + const uint32_t samples = iview->image->info.samples; const uint32_t samples_log2 = ffs(samples) - 1; VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer); uint32_t offset; @@ -849,26 +849,25 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, /* all layers are bound */ if (iview->base_layer > 0) goto fail; - if (iview->image->array_size != iview->layer_count) + if (iview->image->info.array_size != iview->layer_count) goto fail; - if (iview->image->levels > 1) + if (iview->image->info.levels > 1) goto fail; if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D) goto fail; - if (!radv_image_extent_compare(iview->image, &iview->extent)) goto fail; if (clear_rect->rect.offset.x || clear_rect->rect.offset.y || - clear_rect->rect.extent.width != iview->image->extent.width || - clear_rect->rect.extent.height != iview->image->extent.height) + clear_rect->rect.extent.width != iview->image->info.width || + clear_rect->rect.extent.height != iview->image->info.height) goto fail; if (clear_rect->baseArrayLayer != 0) goto fail; - if (clear_rect->layerCount != iview->image->array_size) + if (clear_rect->layerCount != iview->image->info.array_size) goto fail; /* DCC */ @@ -1178,7 +1177,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, const VkImageSubresourceRange *range = &ranges[r]; for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) { const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ? - radv_minify(image->extent.depth, range->baseMipLevel + l) : + radv_minify(image->info.depth, range->baseMipLevel + l) : radv_get_layerCount(image, range); for (uint32_t s = 0; s < layer_count; ++s) { diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index 54dadde788d..838aa933bd0 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -118,7 +118,7 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, /* The Vulkan 1.0 spec says "dstImage must have a sample count equal to * VK_SAMPLE_COUNT_1_BIT." */ - assert(image->samples == 1); + assert(image->info.samples == 1); if (cs) radv_meta_begin_bufimage(cmd_buffer, &saved_state.compute); @@ -337,7 +337,7 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer, * vkCmdCopyImage can be used to copy image data between multisample * images, but both images must have the same number of samples. */ - assert(src_image->samples == dest_image->samples); + assert(src_image->info.samples == dest_image->info.samples); if (cs) radv_meta_begin_itoi(cmd_buffer, &saved_state.compute); else @@ -447,8 +447,8 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer, image_copy.dstSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT; image_copy.dstSubresource.layerCount = 1; - image_copy.extent.width = image->extent.width; - image_copy.extent.height = image->extent.height; + image_copy.extent.width = image->info.width; + image_copy.extent.height = image->info.height; image_copy.extent.depth = 1; meta_copy_image(cmd_buffer, image, linear_image, diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c index b003abba983..1f1ff9db423 100644 --- a/src/amd/vulkan/radv_meta_decompress.c +++ b/src/amd/vulkan/radv_meta_decompress.c @@ -292,9 +292,9 @@ static void radv_process_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_pass_state saved_pass_state; VkDevice device_h = radv_device_to_handle(cmd_buffer->device); VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer); - uint32_t width = radv_minify(image->extent.width, + uint32_t width = radv_minify(image->info.width, subresourceRange->baseMipLevel); - uint32_t height = radv_minify(image->extent.height, + uint32_t height = radv_minify(image->info.height, subresourceRange->baseMipLevel); if (!image->surface.htile_size) diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index 254964287d7..c93901e7008 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -378,8 +378,8 @@ radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, .pAttachments = (VkImageView[]) { radv_image_view_to_handle(&iview) }, - .width = image->extent.width, - .height = image->extent.height, + .width = image->info.width, + .height = image->info.height, .layers = 1 }, &cmd_buffer->pool->alloc, @@ -396,8 +396,8 @@ radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, 0, }, .extent = { - image->extent.width, - image->extent.height, + image->info.width, + image->info.height, } }, .clearValueCount = 0, @@ -406,7 +406,7 @@ radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, VK_SUBPASS_CONTENTS_INLINE); emit_fast_clear_flush(cmd_buffer, - &(VkExtent2D) { image->extent.width, image->extent.height }, + &(VkExtent2D) { image->info.width, image->info.height }, image->fmask.size > 0); radv_CmdEndRenderPass(cmd_buffer_h); diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 460a0bcb517..784d39b58af 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -331,9 +331,9 @@ void radv_CmdResolveImage( regions[0].dstOffset.z) use_compute_resolve = true; - if (regions[0].extent.width != src_image->extent.width || - regions[0].extent.height != src_image->extent.height || - regions[0].extent.depth != src_image->extent.depth) + if (regions[0].extent.width != src_image->info.width || + regions[0].extent.height != src_image->info.height || + regions[0].extent.depth != src_image->info.depth) use_compute_resolve = true; } else use_compute_resolve = true; @@ -351,10 +351,10 @@ void radv_CmdResolveImage( radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer); - assert(src_image->samples > 1); - assert(dest_image->samples == 1); + assert(src_image->info.samples > 1); + assert(dest_image->info.samples == 1); - if (src_image->samples >= 16) { + if (src_image->info.samples >= 16) { /* See commit aa3f9aaf31e9056a255f9e0472ebdfdaa60abe54 for the * glBlitFramebuffer workaround for samples >= 16. */ @@ -362,7 +362,7 @@ void radv_CmdResolveImage( "samples >= 16"); } - if (src_image->array_size > 1) + if (src_image->info.array_size > 1) radv_finishme("vkCmdResolveImage: multisample array images"); if (dest_image->surface.dcc_size) { @@ -457,9 +457,9 @@ void radv_CmdResolveImage( radv_image_view_to_handle(&src_iview), radv_image_view_to_handle(&dest_iview), }, - .width = radv_minify(dest_image->extent.width, + .width = radv_minify(dest_image->info.width, region->dstSubresource.mipLevel), - .height = radv_minify(dest_image->extent.height, + .height = radv_minify(dest_image->info.height, region->dstSubresource.mipLevel), .layers = 1 }, diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index ffa07cac5f1..dc4a1bb53d1 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -325,7 +325,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, { struct radv_device *device = cmd_buffer->device; struct radv_meta_saved_compute_state saved_state; - const uint32_t samples = src_image->samples; + const uint32_t samples = src_image->info.samples; const uint32_t samples_log2 = ffs(samples) - 1; for (uint32_t r = 0; r < region_count; ++r) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 48d0f443e16..77592de3bdb 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1146,10 +1146,7 @@ struct radv_image { */ VkFormat vk_format; VkImageAspectFlags aspects; - VkExtent3D extent; - uint32_t levels; - uint32_t array_size; - uint32_t samples; /**< VkImageCreateInfo::samples */ + struct radeon_surf_info info; VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */ VkImageTiling tiling; /** VkImageCreateInfo::tiling */ VkImageCreateFlags flags; /** VkImageCreateInfo::flags */ @@ -1190,7 +1187,7 @@ radv_get_layerCount(const struct radv_image *image, const VkImageSubresourceRange *range) { return range->layerCount == VK_REMAINING_ARRAY_LAYERS ? - image->array_size - range->baseArrayLayer : range->layerCount; + image->info.array_size - range->baseArrayLayer : range->layerCount; } static inline uint32_t @@ -1198,7 +1195,7 @@ radv_get_levelCount(const struct radv_image *image, const VkImageSubresourceRange *range) { return range->levelCount == VK_REMAINING_MIP_LEVELS ? - image->levels - range->baseMipLevel : range->levelCount; + image->info.levels - range->baseMipLevel : range->levelCount; } struct radeon_bo_metadata; @@ -1288,7 +1285,9 @@ static inline bool radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent) { - if (memcmp(extent, &image->extent, sizeof(*extent))) + if (extent->width != image->info.width || + extent->height != image->info.height || + extent->depth != image->info.depth) return false; return true; } diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index f6bab7410d3..d934e0a568d 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -155,6 +155,15 @@ struct radeon_info { #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) +struct radeon_surf_info { + uint32_t width; + uint32_t height; + uint32_t depth; + uint32_t samples; + uint32_t array_size; + uint32_t levels; +}; + struct radeon_surf_level { uint64_t offset; uint64_t slice_size; |