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authorAnuj Phogat <[email protected]>2017-05-16 10:15:17 -0700
committerAnuj Phogat <[email protected]>2017-06-09 16:02:59 -0700
commit111881abac0dda73a20e491a219a1d7db6512f82 (patch)
tree6e36fc165748c62986ca425917065172f7bed400
parent30e749c8f1cae530fbb7d24e1c5e7097f7cd1821 (diff)
i965/cnl: Handle gen10 in switch cases across the driver
V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec() gen10_init_atoms() (Jason) Remove Vulkan changes. Do them later in a separate patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
-rw-r--r--src/intel/common/gen_l3_config.c1
-rw-r--r--src/intel/compiler/brw_eu.c2
-rw-r--r--src/intel/compiler/brw_eu_compact.c1
-rw-r--r--src/intel/isl/isl.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_formatquery.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_screen.c1
8 files changed, 24 insertions, 1 deletions
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 2520838e7d9..ae31d08bdf3 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -116,6 +116,7 @@ get_l3_configs(const struct gen_device_info *devinfo)
return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
case 9:
+ case 10:
return chv_l3_configs;
default:
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index f5202a05ebe..0ef52e219ca 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -412,6 +412,7 @@ enum gen {
GEN75 = (1 << 5),
GEN8 = (1 << 6),
GEN9 = (1 << 7),
+ GEN10 = (1 << 8),
GEN_ALL = ~0
};
@@ -688,6 +689,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
+ case 10: return GEN10;
default:
unreachable("not reached");
}
diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c
index b2af76d533a..740a395f786 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1362,6 +1362,7 @@ brw_init_compaction_tables(const struct gen_device_info *devinfo)
assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
switch (devinfo->gen) {
+ case 10:
case 9:
case 8:
control_index_table = gen8_control_index_table;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 60a594394b9..860fc28b274 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1778,6 +1778,9 @@ isl_surf_fill_state_s(const struct isl_device *dev, void *state,
case 9:
isl_gen9_surf_fill_state_s(dev, state, info);
break;
+ case 10:
+ isl_gen10_surf_fill_state_s(dev, state, info);
+ break;
default:
assert(!"Cannot fill surface state for this gen");
}
@@ -1809,6 +1812,9 @@ isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
case 9:
isl_gen9_buffer_fill_state_s(state, info);
break;
+ case 10:
+ isl_gen10_buffer_fill_state_s(state, info);
+ break;
default:
assert(!"Cannot fill surface state for this gen");
}
@@ -1876,6 +1882,9 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
case 9:
isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
break;
+ case 10:
+ isl_gen10_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
default:
assert(!"Cannot fill surface state for this gen");
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index d14050c3334..70aecfba19b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -109,6 +109,12 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.mocs.vb = SKL_MOCS_WB;
brw->blorp.exec = gen9_blorp_exec;
break;
+ case 10:
+ brw->blorp.mocs.tex = SKL_MOCS_WB;
+ brw->blorp.mocs.rb = SKL_MOCS_PTE;
+ brw->blorp.mocs.vb = SKL_MOCS_WB;
+ brw->blorp.exec = gen10_blorp_exec;
+ break;
default:
unreachable("Invalid gen");
}
diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c b/src/mesa/drivers/dri/i965/brw_formatquery.c
index 96cc6e04ee7..5faf91fa9e7 100644
--- a/src/mesa/drivers/dri/i965/brw_formatquery.c
+++ b/src/mesa/drivers/dri/i965/brw_formatquery.c
@@ -37,6 +37,7 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum target,
(void) internalFormat;
switch (brw->gen) {
+ case 10:
case 9:
samples[0] = 16;
samples[1] = 8;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 4647f1c41e0..9a858e64a2e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -136,7 +136,9 @@ void brw_init_state( struct brw_context *brw )
brw_init_caches(brw);
- if (brw->gen >= 9)
+ if (brw->gen >= 10)
+ gen10_init_atoms(brw);
+ else if (brw->gen >= 9)
gen9_init_atoms(brw);
else if (brw->gen >= 8)
gen8_init_atoms(brw);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 1c46f8e742d..fec4feabaff 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1852,6 +1852,7 @@ set_max_gl_versions(struct intel_screen *screen)
const bool has_astc = screen->devinfo.gen >= 9;
switch (screen->devinfo.gen) {
+ case 10:
case 9:
case 8:
dri_screen->max_gl_core_version = 45;