diff options
| author | Tom Stellard <[email protected]> | 2012-07-10 08:51:31 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-11 17:47:20 +0000 |
| commit | bbdf3af8577ca61fc54c4a1615e80940c904636e (patch) | |
| tree | aa5cad92a40ac033ec56bf1187617104329ea4a1 | |
| parent | d36499aa62f42192356fd9e34009905ae0e9e6c8 (diff) | |
radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.
The IMM bit is already being set in SICodeEmitter.
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrInfo.td | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.td b/src/gallium/drivers/radeon/SIInstrInfo.td index 30c9c3377ad..be08e8abbce 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.td +++ b/src/gallium/drivers/radeon/SIInstrInfo.td @@ -448,7 +448,6 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU let mayStore = 1; } -/*XXX: We should be able to infer the imm bit based on the arg types */ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass, ValueType vt> { @@ -458,9 +457,7 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass, (ins SMRDmemrr:$src0), asm, [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))] - > { - let IMM = 0; - } + >; def _IMM : SMRD < op, @@ -468,9 +465,7 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass, (ins SMRDmemri:$src0), asm, [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))] - > { - let IMM = 1; - } + >; } include "SIInstrFormats.td" |