diff options
| author | Tom Stellard <[email protected]> | 2012-08-02 14:14:22 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-02 20:12:11 +0000 |
| commit | 4a89a207179d8cf25f259aba8e6c867de42bae54 (patch) | |
| tree | 2f6d863dd4e7e11094a1ea9967a8b0b39dc212b1 | |
| parent | a35eea786823f0130b925cb25486d7d162f2d68c (diff) | |
radeon/llvm: Add support for more f32 CMP instructions on SI
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index c753943eabf..a91606ed6be 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -118,14 +118,24 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; //def EXP : EXP_ <0x00000000, "EXP", []>; defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32", []>; -defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", []>; +defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", + [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))] +>; defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))] >; -defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", []>; -defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", []>; -defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", []>; -defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", []>; +defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", + [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))] +>; +defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", + [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))] +>; +defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", + [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))] +>; +defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", + [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))] +>; defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", []>; defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", []>; defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32", []>; |