diff options
| author | Matt Turner <[email protected]> | 2013-04-09 17:56:19 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2013-05-06 10:17:14 -0700 |
| commit | fa958182b7e7a9a177ec45ffd39d42f15ca756b3 (patch) | |
| tree | 98dd5d1c424e148145547c3961526b90035c3bfb | |
| parent | c71bee757b52c1e222a4e461f12a93d09998e3da (diff) | |
i965: Add support for emitting and disassembling bit instructions.
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
Reviewed-by: Chris Forbes <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_disasm.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu.h | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 7 |
4 files changed, 28 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index b0075202171..e37805d4ad6 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -647,6 +647,10 @@ enum opcode { BRW_OPCODE_CMPN = 17, BRW_OPCODE_F32TO16 = 19, BRW_OPCODE_F16TO32 = 20, + BRW_OPCODE_BFREV = 23, + BRW_OPCODE_BFE = 24, + BRW_OPCODE_BFI1 = 25, + BRW_OPCODE_BFI2 = 26, BRW_OPCODE_JMPI = 32, BRW_OPCODE_IF = 34, BRW_OPCODE_IFF = 35, @@ -676,6 +680,9 @@ enum opcode { BRW_OPCODE_MAC = 72, BRW_OPCODE_MACH = 73, BRW_OPCODE_LZD = 74, + BRW_OPCODE_FBH = 75, + BRW_OPCODE_FBL = 76, + BRW_OPCODE_CBIT = 77, BRW_OPCODE_SAD2 = 80, BRW_OPCODE_SADA2 = 81, BRW_OPCODE_DP4 = 84, diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 3e7c613eb05..18e6c9d78fc 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -43,6 +43,10 @@ const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1}, + [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1}, + [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1}, + [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1}, [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, @@ -70,6 +74,9 @@ const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1}, + [BRW_OPCODE_BFI1] = { .name = "bfe1", .nsrc = 2, .ndst = 1}, + [BRW_OPCODE_BFI2] = { .name = "bfe2", .nsrc = 3, .ndst = 1}, [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 9683b1314da..ce8843d8a6e 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -176,6 +176,13 @@ ALU2(LINE) ALU2(PLN) ALU3(MAD) ALU3(LRP) +ALU1(BFREV) +ALU3(BFE) +ALU2(BFI1) +ALU3(BFI2) +ALU1(FBH) +ALU1(FBL) +ALU1(CBIT) ROUND(RNDZ) ROUND(RNDE) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index bd02270a173..31d97ca5c28 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -957,6 +957,13 @@ ALU2(LINE) ALU2(PLN) ALU3(MAD) ALU3(LRP) +ALU1(BFREV) +ALU3(BFE) +ALU2(BFI1) +ALU3(BFI2) +ALU1(FBH) +ALU1(FBL) +ALU1(CBIT) ROUND(RNDZ) ROUND(RNDE) |