diff options
| author | Kenneth Graunke <[email protected]> | 2017-08-28 22:00:12 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-08-30 16:59:22 -0700 |
| commit | df8f4bfc02d631412632a8bef537a2e4cec4945b (patch) | |
| tree | 94ec18573b43aa3870a5bff1a9d826ac3c787734 | |
| parent | 225425111fee082e3be14c22c256314b85724ef8 (diff) | |
i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().
Although we're phasing out brw_emit_mi_flush(), we still use it in some
places in order to "flush everything". In a number of those places, we
write data to a buffer that we may then bind as an image surface, SSBO,
or atomic buffer. Those usages require us to flush the data cache.
Reviewed-by: Jason Ekstrand <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 063b814b9a3..460b8f73b6d 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -449,6 +449,7 @@ brw_emit_mi_flush(struct brw_context *brw) if (devinfo->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | + PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |