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authorXiang, Haihao <haihao.xiang@intel.com>2010-12-24 09:34:50 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2010-12-24 09:51:44 +0800
commitdc987adc9f5f9f851be124985fa6bbcdbfa4a7a5 (patch)
tree681e4e49c66923c54b794689d725427a32a74292
parent82493216044b0320219fc631baa7b02381daa0de (diff)
i965: use align1 access mode for instructions with execSize=1 in VS
All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c in oglconform.
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f8a3044dd0a..88131c432ec 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1727,6 +1727,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
/* Setup MRF[1] with location/offset into const buffer */
brw_push_insn_state(p);
+ brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -1774,6 +1775,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
/* Setup MRF[1] with offset into const buffer */
brw_push_insn_state(p);
+ brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);