diff options
| author | Kenneth Graunke <[email protected]> | 2016-08-17 06:35:01 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2016-08-18 00:47:00 -0700 |
| commit | d14dd727f4aded5bd34a78dc2c81374a78114440 (patch) | |
| tree | cb944989fa1956670734067c3d8a9e91d1fc2c22 | |
| parent | 159f0377556c45630cdc0721b193f34217a329b0 (diff) | |
i965: Fix barrier count shift in scalar TCS backend.
The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend
correctly shifts by 9, but the scalar backend only shifted by 8.
It's not like this changed - I think I just made a typo when writing
the original scalar TCS backend code.
Cc: [email protected]
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Alejandro Piñeiro <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index a36765c90c1..c278bd4c00b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2436,7 +2436,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, /* Set the Barrier Count and the enable bit */ chanbld.OR(m0_2, m0_2, - brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15))); + brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15))); bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0); break; |