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authorJason Ekstrand <[email protected]>2017-08-02 12:18:25 -0700
committerEmil Velikov <[email protected]>2017-08-11 20:52:22 +0100
commitb1514579c2a1325db0e10f685ae63ba462aacde6 (patch)
treee7329ce22da060ae29e6cb5141e308b5e065e03f
parentdc63c715cb3f0d7dddb31345689355b1b450cdde (diff)
intel/isl: Don't align the height of the last array slice
We were calculating the total height of 2D surfaces by multiplying the row pitch by the number of slices. This means that we actually request slightly more space than actually needed since the padding on the last slice is unnecessary. For tiled surfaces this is not likely to make a difference. For linear surfaces, on the other hand, this means we may require additional memory. In particular, this makes the i965 driver reject EGL imports of buffers which do not have this extra padding. Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]> (cherry picked from commit 4d27c6095e8385cccd225993452baad4d2e35420)
-rw-r--r--src/intel/isl/isl.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index d3124debfaa..6b4203d79d2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -982,7 +982,8 @@ isl_calc_phys_total_extent_el_gen4_2d(
&phys_slice0_sa);
*total_extent_el = (struct isl_extent2d) {
.w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
- .h = *array_pitch_el_rows * phys_level0_sa->array_len,
+ .h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
+ isl_assert_div(phys_slice0_sa.h, fmtl->bh),
};
}