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authorTim Rowley <[email protected]>2017-03-02 09:43:11 -0800
committerTim Rowley <[email protected]>2017-03-20 18:04:53 -0500
commitab3f4449c37cf991f858a34d283ee8d24cb0725f (patch)
tree29ad58c2d07c74f0ba2c5f7148a0ba05dc7fb3da
parent8cd8240cfce1e26f2f237f1eb98d46ba47bca626 (diff)
swr: [rasterizer jitter] Fix LogicOp blend jit after assert changes
Reviewed-by: Bruce Cherniak <[email protected]>
-rw-r--r--src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp35
1 files changed, 25 insertions, 10 deletions
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
index cbcc3434a16..55961d19957 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
@@ -162,7 +162,7 @@ struct BlendJit : public Builder
switch (type)
{
- case SWR_TYPE_FLOAT:
+ default:
break;
case SWR_TYPE_UNORM:
@@ -179,7 +179,7 @@ struct BlendJit : public Builder
src[3] = VMINPS(VMAXPS(src[3], VIMMED1(-1.0f)), VIMMED1(1.0f));
break;
- default: SWR_INVALID("Unsupport format type: %d", type);
+ case SWR_TYPE_UNKNOWN: SWR_INVALID("Unsupport format type: %d", type);
}
}
@@ -671,10 +671,13 @@ struct BlendJit : public Builder
continue;
}
- if (info.bpc[i] >= 32) {
+ if (info.bpc[i] >= 32)
+ {
vMask[i] = VIMMED1(0xFFFFFFFF);
scale[i] = 0xFFFFFFFF;
- } else {
+ }
+ else
+ {
vMask[i] = VIMMED1((1 << info.bpc[i]) - 1);
if (info.type[i] == SWR_TYPE_SNORM)
scale[i] = (1 << (info.bpc[i] - 1)) - 1;
@@ -682,10 +685,16 @@ struct BlendJit : public Builder
scale[i] = (1 << info.bpc[i]) - 1;
}
- switch (info.type[i]) {
+ switch (info.type[i])
+ {
default:
- SWR_INVALID("Unsupported type for logic op\n");
- /* fallthrough */
+ SWR_INVALID("Unsupported type for logic op: %d", info.type[i]);
+ break;
+
+ case SWR_TYPE_UNKNOWN:
+ case SWR_TYPE_UNUSED:
+ // fallthrough
+
case SWR_TYPE_UINT:
case SWR_TYPE_SINT:
src[i] = BITCAST(src[i], mSimdInt32Ty);
@@ -723,10 +732,16 @@ struct BlendJit : public Builder
// clear upper bits from PS output not in RT format after doing logic op
result[i] = AND(result[i], vMask[i]);
- switch (info.type[i]) {
+ switch (info.type[i])
+ {
default:
- SWR_INVALID("Unsupported type for logic op\n");
- /* fallthrough */
+ SWR_INVALID("Unsupported type for logic op: %d", info.type[i]);
+ break;
+
+ case SWR_TYPE_UNKNOWN:
+ case SWR_TYPE_UNUSED:
+ // fallthrough
+
case SWR_TYPE_UINT:
case SWR_TYPE_SINT:
result[i] = BITCAST(result[i], mSimdFP32Ty);