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authorEric Anholt <[email protected]>2011-01-07 18:18:50 -0800
committerEric Anholt <[email protected]>2011-01-07 18:25:54 -0800
commit29c4f95cbcad29d52bf3b6c875840b38b8823e4c (patch)
tree79ba8faebc6202d9b3272228789a1880627a1742
parent8f593597fc100b496db368b2b988e1d2ec58b612 (diff)
intel: Make renderbuffer tiling choice match texture tiling choice.
There really shouldn't be any difference between the two for us. Fixes a bug where Z16 renderbuffers would be untiled on gen6, likely leading to hangs.
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index f317cdc7b30..efc726e32fa 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -145,10 +145,15 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
DBG("Allocating %d x %d Intel RBO\n", width, height);
tiling = I915_TILING_NONE;
-
- /* Gen6 requires depth must be tiling */
- if (intel->gen >= 6 && rb->Format == MESA_FORMAT_S8_Z24)
- tiling = I915_TILING_Y;
+ if (intel->use_texture_tiling) {
+ GLenum base_format = _mesa_get_format_base_format(rb->Format);
+
+ if (intel->gen >= 4 && (base_format == GL_DEPTH_COMPONENT ||
+ base_format == GL_DEPTH_STENCIL))
+ tiling = I915_TILING_Y;
+ else
+ tiling = I915_TILING_X;
+ }
irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
width, height, GL_TRUE);