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authorDave Airlie <airlied@redhat.com>2011-12-06 14:08:07 +0000
committerDave Airlie <airlied@redhat.com>2011-12-06 15:11:36 +0000
commit1136da9c6bea8f579c0d92e5c263bde83a1fd0cf (patch)
tree3f3fa4e2d727722feed88b45ce6a9159beb3c0b4
parent61a40581d26d17fd9351914b267f364dbb12f8d0 (diff)
r200: add Z16 depth detiling.
This passes readPixSanity with z16 visuals. Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_fbo.c105
1 files changed, 105 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 31203cc1d5c..d8b3b075f14 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -91,6 +91,28 @@ static GLuint r200_depth_4byte(const struct radeon_renderbuffer * rrb,
return offset;
}
+static GLuint r200_depth_2byte(const struct radeon_renderbuffer *rrb,
+ GLint x, GLint y)
+{
+ GLuint offset;
+ GLuint b;
+
+ offset = 0;
+ b = (((y >> 4) * (rrb->pitch >> 7) + (x >> 6)));
+ offset += (b >> 1) << 12;
+ offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
+ offset += ((y >> 2) & 0x3) << 9;
+ offset += ((x >> 3) & 0x1) << 8;
+ offset += ((x >> 4) & 0x3) << 6;
+ offset += ((x >> 2) & 0x1) << 5;
+ offset += ((y >> 1) & 0x1) << 4;
+ offset += ((x >> 1) & 0x1) << 3;
+ offset += (y & 0x1) << 2;
+ offset += (x & 0x1) << 1;
+
+ return offset;
+}
+
static void
radeon_map_renderbuffer_s8z24(struct gl_context *ctx,
struct gl_renderbuffer *rb,
@@ -128,6 +150,44 @@ radeon_map_renderbuffer_s8z24(struct gl_context *ctx,
*out_map = rrb->map_buffer;
*out_stride = rrb->map_pitch;
}
+
+static void
+radeon_map_renderbuffer_z16(struct gl_context *ctx,
+ struct gl_renderbuffer *rb,
+ GLuint x, GLuint y, GLuint w, GLuint h,
+ GLbitfield mode,
+ GLubyte **out_map,
+ GLint *out_stride)
+{
+ struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
+ uint16_t *untiled_z16_map, *tiled_z16_map;
+ int ret;
+ int y_flip = (rb->Name == 0) ? -1 : 1;
+ int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
+ uint32_t pitch = w * rrb->cpp;
+
+ rrb->map_pitch = pitch;
+
+ rrb->map_buffer = malloc(w * h * 2);
+ ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
+
+ untiled_z16_map = rrb->map_buffer;
+ tiled_z16_map = rrb->bo->ptr;
+
+ for (uint32_t pix_y = 0; pix_y < h; ++ pix_y) {
+ for (uint32_t pix_x = 0; pix_x < w; ++pix_x) {
+ uint32_t flipped_y = y_flip * (int32_t)(y + pix_y) + y_bias;
+ uint32_t src_offset = r200_depth_2byte(rrb, x + pix_x, flipped_y);
+ uint32_t dst_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
+ untiled_z16_map[dst_offset/2] = tiled_z16_map[src_offset/2];
+ }
+ }
+
+ radeon_bo_unmap(rrb->bo);
+
+ *out_map = rrb->map_buffer;
+ *out_stride = rrb->map_pitch;
+}
#endif
static void
@@ -219,6 +279,12 @@ radeon_map_renderbuffer(struct gl_context *ctx,
mode, out_map, out_stride);
return;
}
+
+ if (rb->Format == MESA_FORMAT_Z16 && !rrb->has_surface) {
+ radeon_map_renderbuffer_z16(ctx, rb, x, y, w, h,
+ mode, out_map, out_stride);
+ return;
+ }
#endif
ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
assert(!ret);
@@ -275,6 +341,40 @@ radeon_unmap_renderbuffer_s8z24(struct gl_context *ctx,
free(rrb->map_buffer);
rrb->map_buffer = NULL;
}
+
+static void
+radeon_unmap_renderbuffer_z16(struct gl_context *ctx,
+ struct gl_renderbuffer *rb)
+{
+ struct radeon_context *const rmesa = RADEON_CONTEXT(ctx);
+ struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
+
+ if (!rrb->map_buffer)
+ return;
+
+ if (rrb->map_mode & GL_MAP_WRITE_BIT) {
+ uint16_t *untiled_z16_map = rrb->map_buffer;
+ uint16_t *tiled_z16_map;
+ int y_flip = (rb->Name == 0) ? -1 : 1;
+ int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
+
+ radeon_bo_map(rrb->bo, 1);
+
+ tiled_z16_map = rrb->bo->ptr;
+
+ for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) {
+ for (uint32_t pix_x = 0; pix_x < rrb->map_w; pix_x++) {
+ uint32_t flipped_y = y_flip * (int32_t)(pix_y + rrb->map_y) + y_bias;
+ uint32_t dst_offset = r200_depth_2byte(rrb, rrb->map_x + pix_x, flipped_y);
+ uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
+ tiled_z16_map[dst_offset/2] = untiled_z16_map[src_offset/2];
+ }
+ }
+ radeon_bo_unmap(rrb->bo);
+ }
+ free(rrb->map_buffer);
+ rrb->map_buffer = NULL;
+}
#endif
static void
@@ -290,6 +390,11 @@ radeon_unmap_renderbuffer(struct gl_context *ctx,
radeon_unmap_renderbuffer_s8z24(ctx, rb);
return;
}
+
+ if (rb->Format == MESA_FORMAT_Z16 && !rrb->has_surface) {
+ radeon_unmap_renderbuffer_z16(ctx, rb);
+ return;
+ }
#endif
if (!rrb->map_bo) {