diff options
| author | Rob Clark <[email protected]> | 2013-08-20 13:46:30 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2013-08-24 13:23:32 -0400 |
| commit | 8b250bb8aa31b781681491b1d2a8baa15a024c1c (patch) | |
| tree | 39fbba9ac498488436d757025583aadb8975b6f6 | |
| parent | 528bee59feb6463073bb5da13df00e79037b1877 (diff) | |
freedreno/a3xx/compiler: fix CMP
The 1st src to add.s needs (r) flag (repeat), otherwise it will end up:
add.s dst.xyzw, tmp.xxxx -1
instead of:
add.s dst.xyzw, tmp.xyzw, -1
Also, if we are using a temporary dst to avoid clobbering one of the src
registers, we actually need to use that as the dst for the sel
instruction.
Signed-off-by: Rob Clark <[email protected]>
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_compiler.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c index eabe21cb7e9..07bede4a4c8 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c @@ -790,13 +790,13 @@ trans_cmp(const struct instr_translater *t, instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S); instr->repeat = 3; add_dst_reg(ctx, instr, &tmp_dst, 0); - add_src_reg(ctx, instr, &tmp_src, 0); + add_src_reg(ctx, instr, &tmp_src, 0)->flags |= IR3_REG_R; ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1; /* sel.{f32,f16} dst, src2, tmp, src1 */ instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32); - vectorize(ctx, instr, &inst->Dst[0].Register, 3, + vectorize(ctx, instr, dst, 3, &inst->Src[2].Register, 0, &tmp_src, 0, &inst->Src[1].Register, 0); |