i965/gen7+: Disentangle MSAA layout from fast clear state.

This patch renames the enum that's used to keep track of fast clear
state from "mcs_state" to "fast_clear_state", and it removes the enum
value INTEL_MCS_STATE_MSAA (which previously meant, "this is an MSAA
buffer, so we're not keeping track of fast clear state").  The only
real purpose that enum value was serving was to prevent us from trying
to do fast clear resolves on MSAA buffers, and it's just as easy to
prevent that by checking the buffer's msaa_layout.

This paves the way for implementing fast clears of MSAA buffers.

Reviewed-by: Chad Versace <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

3 files changed, 47 insertions, 48 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 3af22b6075e..01a911b0e79 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -250,8 +250,8 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
     * never larger than the size of a tile, so there is no danger of
     * overflowing beyond the memory belonging to the region.
     */
-   if (irb->mt->mcs_state != INTEL_MCS_STATE_NONE && !partial_clear &&
-       wm_prog_key.use_simd16_replicated_data &&
+   if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
+       !partial_clear && wm_prog_key.use_simd16_replicated_data &&
        is_color_fast_clear_compatible(brw, format, &ctx->Color.ClearColor)) {
       memset(push_consts, 0xff, 4*sizeof(float));
       fast_clear_op = GEN7_FAST_CLEAR_OP_FAST_CLEAR;
@@ -471,10 +471,10 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
          brw->state.dirty.brw |= BRW_NEW_SURFACES;
       }
 
-      /* If the buffer is already in INTEL_MCS_STATE_CLEAR, the clear is
-       * redundant and can be skipped.
+      /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
+       * is redundant and can be skipped.
        */
-      if (irb->mt->mcs_state == INTEL_MCS_STATE_CLEAR)
+      if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
          return true;
 
       /* If the MCS buffer hasn't been allocated yet, we need to allocate
@@ -499,10 +499,10 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
 
    if (is_fast_clear) {
       /* Now that the fast clear has occurred, put the buffer in
-       * INTEL_MCS_STATE_CLEAR so that we won't waste time doing redundant
-       * clears.
+       * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
+       * redundant clears.
        */
-      irb->mt->mcs_state = INTEL_MCS_STATE_CLEAR;
+      irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
    }
 
    return true;
@@ -563,7 +563,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
 
    brw_blorp_rt_resolve_params params(brw, mt);
    brw_blorp_exec(brw, &params);
-   mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
+   mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 }
 
 } /* extern "C" */
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 280abb7a689..a96c7ea2f83 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -250,7 +250,7 @@ intel_miptree_create_layout(struct brw_context *brw,
    mt->logical_width0 = width0;
    mt->logical_height0 = height0;
    mt->logical_depth0 = depth0;
-   mt->mcs_state = INTEL_MCS_STATE_NONE;
+   mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
 
    /* The cpp is bytes per (1, blockheight)-sized block for compressed
     * textures.  This is why you'll see divides by blockheight all over
@@ -604,12 +604,12 @@ intel_miptree_create(struct brw_context *brw,
    }
 
    /* If this miptree is capable of supporting fast color clears, set
-    * mcs_state appropriately to ensure that fast clears will occur.
+    * fast_clear_state appropriately to ensure that fast clears will occur.
     * Allocation of the MCS miptree will be deferred until the first fast
     * clear actually occurs.
     */
    if (intel_is_non_msrt_mcs_buffer_supported(brw, mt))
-      mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
+      mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 
    return mt;
 }
@@ -705,12 +705,12 @@ intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
    singlesample_mt->region->name = region->name;
 
    /* If this miptree is capable of supporting fast color clears, set
-    * mcs_state appropriately to ensure that fast clears will occur.
+    * fast_clear_state appropriately to ensure that fast clears will occur.
     * Allocation of the MCS miptree will be deferred until the first fast
     * clear actually occurs.
     */
    if (intel_is_non_msrt_mcs_buffer_supported(brw, singlesample_mt))
-      singlesample_mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
+      singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 
    if (num_samples == 0)
       return singlesample_mt;
@@ -1233,7 +1233,6 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
     *
     *     "The MCS surface must be stored as Tile Y."
     */
-   mt->mcs_state = INTEL_MCS_STATE_MSAA;
    mt->mcs_mt = intel_miptree_create(brw,
                                      mt->target,
                                      format,
@@ -1259,6 +1258,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
    void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
    memset(data, 0xff, mt->mcs_mt->region->bo->size);
    intel_miptree_unmap_raw(brw, mt->mcs_mt);
+   mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
 
    return mt->mcs_mt;
 }
@@ -1511,15 +1511,16 @@ void
 intel_miptree_resolve_color(struct brw_context *brw,
                             struct intel_mipmap_tree *mt)
 {
-   switch (mt->mcs_state) {
-   case INTEL_MCS_STATE_NONE:
-   case INTEL_MCS_STATE_MSAA:
-   case INTEL_MCS_STATE_RESOLVED:
+   switch (mt->fast_clear_state) {
+   case INTEL_FAST_CLEAR_STATE_NO_MCS:
+   case INTEL_FAST_CLEAR_STATE_RESOLVED:
       /* No resolve needed */
       break;
-   case INTEL_MCS_STATE_UNRESOLVED:
-   case INTEL_MCS_STATE_CLEAR:
-      brw_blorp_resolve_color(brw, mt);
+   case INTEL_FAST_CLEAR_STATE_UNRESOLVED:
+   case INTEL_FAST_CLEAR_STATE_CLEAR:
+      /* Fast color clear resolves only make sense for non-MSAA buffers. */
+      if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE)
+         brw_blorp_resolve_color(brw, mt);
       break;
    }
 }
@@ -1530,9 +1531,9 @@ intel_miptree_resolve_color(struct brw_context *brw,
  * process or another miptree.
  *
  * Fast color clears are unsafe with shared buffers, so we need to resolve and
- * then discard the MCS buffer, if present.  We also set the mcs_state to
- * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
- * future.
+ * then discard the MCS buffer, if present.  We also set the fast_clear_state
+ * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
+ * allocated in the future.
  */
 void
 intel_miptree_make_shareable(struct brw_context *brw,
@@ -1548,7 +1549,7 @@ intel_miptree_make_shareable(struct brw_context *brw,
    if (mt->mcs_mt) {
       intel_miptree_resolve_color(brw, mt);
       intel_miptree_release(&mt->mcs_mt);
-      mt->mcs_state = INTEL_MCS_STATE_NONE;
+      mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 79cef358443..cde702c3c4a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -203,8 +203,8 @@ enum intel_msaa_layout
 
 
 /**
- * Enum for keeping track of the state of an MCS buffer associated with a
- * miptree.  This determines when fast clear related operations are needed.
+ * Enum for keeping track of the fast clear state of a buffer associated with
+ * a miptree.
  *
  * Fast clear works by deferring the memory writes that would be used to clear
  * the buffer, so that instead of performing them at the time of the clear
@@ -212,23 +212,18 @@ enum intel_msaa_layout
  * buffer is later accessed for rendering.  The MCS buffer keeps track of
  * which regions of the buffer still have pending clear writes.
  *
- * This enum keeps track of the driver's knowledge of the state of the MCS
- * buffer.
+ * This enum keeps track of the driver's knowledge of pending fast clears in
+ * the MCS buffer.
  *
  * MCS buffers only exist on Gen7+.
  */
-enum intel_mcs_state
+enum intel_fast_clear_state
 {
    /**
     * There is no MCS buffer for this miptree, and one should never be
     * allocated.
     */
-   INTEL_MCS_STATE_NONE,
-
-   /**
-    * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
-    */
-   INTEL_MCS_STATE_MSAA,
+   INTEL_FAST_CLEAR_STATE_NO_MCS,
 
    /**
     * No deferred clears are pending for this miptree, and the contents of the
@@ -239,8 +234,11 @@ enum intel_mcs_state
     *
     * In this state, the color buffer can be used for purposes other than
     * rendering without needing a render target resolve.
+    *
+    * Since there is no such thing as a "fast color clear resolve" for MSAA
+    * buffers, an MSAA buffer will never be in this state.
     */
-   INTEL_MCS_STATE_RESOLVED,
+   INTEL_FAST_CLEAR_STATE_RESOLVED,
 
    /**
     * An MCS buffer exists for this miptree, and deferred clears are pending
@@ -248,23 +246,23 @@ enum intel_mcs_state
     * The contents of the color buffer are only correct for the regions where
     * the MCS buffer doesn't indicate a deferred clear.
     *
-    * In this state, a render target resolve must be performed before the
-    * color buffer can be used for purposes other than rendering.
+    * If a single-sample buffer is in this state, a render target resolve must
+    * be performed before it can be used for purposes other than rendering.
     */
-   INTEL_MCS_STATE_UNRESOLVED,
+   INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 
    /**
     * An MCS buffer exists for this miptree, and deferred clears are pending
     * for the entire color buffer, and the contents of the MCS buffer reflect
     * this.  The contents of the color buffer are undefined.
     *
-    * In this state, a render target resolve must be performed before the
-    * color buffer can be used for purposes other than rendering.
+    * If a single-sample buffer is in this state, a render target resolve must
+    * be performed before it can be used for purposes other than rendering.
     *
     * If the client attempts to clear a buffer which is already in this state,
     * the clear can be safely skipped, since the buffer is already clear.
     */
-   INTEL_MCS_STATE_CLEAR,
+   INTEL_FAST_CLEAR_STATE_CLEAR,
 };
 
 struct intel_mipmap_tree
@@ -452,9 +450,9 @@ struct intel_mipmap_tree
    struct intel_mipmap_tree *mcs_mt;
 
    /**
-    * MCS state for this buffer.
+    * Fast clear state for this buffer.
     */
-   enum intel_mcs_state mcs_state;
+   enum intel_fast_clear_state fast_clear_state;
 
    /**
     * The SURFACE_STATE bits associated with the last fast color clear to this
@@ -687,8 +685,8 @@ intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
     * unresolved state, since it won't be guaranteed to be clear after
     * rendering occurs.
     */
-   if (mt->mcs_state == INTEL_MCS_STATE_CLEAR)
-      mt->mcs_state = INTEL_MCS_STATE_UNRESOLVED;
+   if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
+      mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 }
 
 void