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authorKenneth Graunke <[email protected]>2013-12-11 15:54:07 -0800
committerKenneth Graunke <[email protected]>2014-01-20 15:38:24 -0800
commit23827756f3198054ba9c812b6294e5317871f223 (patch)
tree521d50014a93ef1ba478ae5ccd709e9171e7092f
parentf7e76e00b6d476ad045a70db34908cce31e767fa (diff)
i965: Update PIPE_CONTROL packet lengths for Broadwell.
On Broadwell, PIPE_CONTROL needs an extra DWord to accomodate the 48-bit addressing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index d1587cba10c..caec3125565 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -440,7 +440,16 @@ intel_batchbuffer_data(struct brw_context *brw,
void
brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
{
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(6);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(flags);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ } else if (brw->gen >= 6) {
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
@@ -471,7 +480,16 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
drm_intel_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper)
{
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(6);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(flags);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ OUT_BATCH(imm_lower);
+ OUT_BATCH(imm_upper);
+ ADVANCE_BATCH();
+ } else if (brw->gen >= 6) {
/* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
* on later platforms. We always use PPGTT on Gen7+.
*/