diff options
| author | Marek Olšák <[email protected]> | 2012-01-30 09:02:30 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2012-01-31 23:12:30 +0100 |
| commit | 1c5625cdb96332a746c9eebe042a3a9dbe844351 (patch) | |
| tree | 6a7ea3560d59da76f7e50595280e9af8f412b191 | |
| parent | 0671400dcc72553b5f9719639e86069a1734dbe5 (diff) | |
r600g: remove unused r600_reg::flush_mask
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_hw_context.c | 1593 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_hw_context.c | 761 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_hw_context_priv.h | 1 |
3 files changed, 1176 insertions, 1179 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 8fc83512a37..443bc7c6743 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -33,813 +33,813 @@ #define GROUP_FORCE_NEW_BLOCK 0 static const struct r600_reg evergreen_config_reg_list[] = { - {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C0C_SQ_GPR_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008E2C_SQ_LDS_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0}, + {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C0C_SQ_GPR_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008E2C_SQ_LDS_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, }; static const struct r600_reg cayman_config_reg_list[] = { - {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0}, + {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, }; static const struct r600_reg evergreen_ctl_const_list[] = { - {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0}, }; static const struct r600_reg evergreen_context_reg_list[] = { - {R_028000_DB_RENDER_CONTROL, 0, 0, 0}, - {R_028004_DB_COUNT_CONTROL, 0, 0, 0}, - {R_028008_DB_DEPTH_VIEW, 0, 0, 0}, - {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, - {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028044_DB_STENCIL_INFO, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028058_DB_DEPTH_SIZE, 0, 0, 0}, - {R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, - {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0, 0}, - {R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {R_028350_SX_MISC, 0, 0, 0}, - {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {R_028414_CB_BLEND_RED, 0, 0, 0}, - {R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {R_028438_SX_ALPHA_REF, 0, 0, 0}, - {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, - {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, - {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, - {R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, - {R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, - {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, - {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, - {R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, - {R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, - {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, - {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, - {R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, - {R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, - {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, - {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, - {R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, - {R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, - {R_028600_PA_CL_UCP4_Y, 0, 0, 0}, - {R_028604_PA_CL_UCP4_Z, 0, 0, 0}, - {R_028608_PA_CL_UCP4_W, 0, 0, 0}, - {R_02860C_PA_CL_UCP5_X, 0, 0, 0}, - {R_028610_PA_CL_UCP5_Y, 0, 0, 0}, - {R_028614_PA_CL_UCP5_Z, 0, 0, 0}, - {R_028618_PA_CL_UCP5_W, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, - {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, - {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, - {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, - {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, - {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, - {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, - {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, - {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, - {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, - {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, - {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, - {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, - {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0, 0}, - {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, - {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0, 0}, - {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, - {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0, 0}, - {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, - {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, - {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, - {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, - {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {R_028A0C_PA_SC_LINE_STIPPLE, 0 ,0, 0}, - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {R_028A40_VGT_GS_MODE, 0, 0, 0}, - {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, - {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, - {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, - {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, - {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, - {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, - {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, - {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, - {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, - {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0, 0}, - {R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, - {R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, - {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, - {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028C78_CB_COLOR0_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, - {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, - {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, - {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, - {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, - {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, - {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, - {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, - {R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, - {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, - {R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, - {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, - {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028D68_CB_COLOR4_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, - {R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, - {R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, - {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, - {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, - {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, - {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, - {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, - {R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, - {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, - {R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, - {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, - {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E58_CB_COLOR8_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, - {R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, - {R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, - {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E74_CB_COLOR9_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, - {R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, - {R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, - {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E90_CB_COLOR10_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, - {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, - {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, - {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, + {R_028000_DB_RENDER_CONTROL, 0, 0}, + {R_028004_DB_COUNT_CONTROL, 0, 0}, + {R_028008_DB_DEPTH_VIEW, 0, 0}, + {R_02800C_DB_RENDER_OVERRIDE, 0, 0}, + {R_028010_DB_RENDER_OVERRIDE2, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028044_DB_STENCIL_INFO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028058_DB_DEPTH_SIZE, 0, 0}, + {R_02805C_DB_DEPTH_SLICE, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0}, + {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0}, + {R_02823C_CB_SHADER_MASK, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0}, + {R_028350_SX_MISC, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0}, + {R_0285BC_PA_CL_UCP0_X, 0, 0}, + {R_0285C0_PA_CL_UCP0_Y, 0, 0}, + {R_0285C4_PA_CL_UCP0_Z, 0, 0}, + {R_0285C8_PA_CL_UCP0_W, 0, 0}, + {R_0285CC_PA_CL_UCP1_X, 0, 0}, + {R_0285D0_PA_CL_UCP1_Y, 0, 0}, + {R_0285D4_PA_CL_UCP1_Z, 0, 0}, + {R_0285D8_PA_CL_UCP1_W, 0, 0}, + {R_0285DC_PA_CL_UCP2_X, 0, 0}, + {R_0285E0_PA_CL_UCP2_Y, 0, 0}, + {R_0285E4_PA_CL_UCP2_Z, 0, 0}, + {R_0285E8_PA_CL_UCP2_W, 0, 0}, + {R_0285EC_PA_CL_UCP3_X, 0, 0}, + {R_0285F0_PA_CL_UCP3_Y, 0, 0}, + {R_0285F4_PA_CL_UCP3_Z, 0, 0}, + {R_0285F8_PA_CL_UCP3_W, 0, 0}, + {R_0285FC_PA_CL_UCP4_X, 0, 0}, + {R_028600_PA_CL_UCP4_Y, 0, 0}, + {R_028604_PA_CL_UCP4_Z, 0, 0}, + {R_028608_PA_CL_UCP4_W, 0, 0}, + {R_02860C_PA_CL_UCP5_X, 0, 0}, + {R_028610_PA_CL_UCP5_Y, 0, 0}, + {R_028614_PA_CL_UCP5_Z, 0, 0}, + {R_028618_PA_CL_UCP5_W, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_1, 0, 0}, + {R_028624_SPI_VS_OUT_ID_2, 0, 0}, + {R_028628_SPI_VS_OUT_ID_3, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_4, 0, 0}, + {R_028630_SPI_VS_OUT_ID_5, 0, 0}, + {R_028634_SPI_VS_OUT_ID_6, 0, 0}, + {R_028638_SPI_VS_OUT_ID_7, 0, 0}, + {R_02863C_SPI_VS_OUT_ID_8, 0, 0}, + {R_028640_SPI_VS_OUT_ID_9, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0}, + {R_0286E0_SPI_BARYC_CNTL, 0, 0}, + {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0}, + {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0}, + {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, + {R_028844_SQ_PGM_RESOURCES_PS, 0, 0}, + {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0}, + {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0}, + {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0}, + {R_028860_SQ_PGM_RESOURCES_VS, 0, 0}, + {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0}, + {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0}, + {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0}, + {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0}, + {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0}, + {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0}, + {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0}, + {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0}, + {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0}, + {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0}, + {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0}, + {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0}, + {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0}, + {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0}, + {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0}, + {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0}, + {R_028A48_PA_SC_MODE_CNTL_0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0}, + {R_028ABC_DB_HTILE_SURFACE, 0, 0}, + {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0}, + {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0}, + {R_028AC8_DB_PRELOAD_CONTROL, 0, 0}, + {R_028B54_VGT_SHADER_STAGES_EN, 0, 0}, + {R_028B70_DB_ALPHA_TO_MASK, 0, 0}, + {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0}, + {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0}, + {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0}, + {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0}, + {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0}, + {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0}, + {R_028B94_VGT_STRMOUT_CONFIG, 0, 0}, + {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0}, + {R_028C3C_PA_SC_AA_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0}, + {R_028C64_CB_COLOR0_PITCH, 0, 0}, + {R_028C68_CB_COLOR0_SLICE, 0, 0}, + {R_028C6C_CB_COLOR0_VIEW, 0, 0}, + {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0}, + {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028C78_CB_COLOR0_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0}, + {R_028CA0_CB_COLOR1_PITCH, 0, 0}, + {R_028CA4_CB_COLOR1_SLICE, 0, 0}, + {R_028CA8_CB_COLOR1_VIEW, 0, 0}, + {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0}, + {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028CB4_CB_COLOR1_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0}, + {R_028CDC_CB_COLOR2_PITCH, 0, 0}, + {R_028CE0_CB_COLOR2_SLICE, 0, 0}, + {R_028CE4_CB_COLOR2_VIEW, 0, 0}, + {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0}, + {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028CF0_CB_COLOR2_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D18_CB_COLOR3_PITCH, 0, 0}, + {R_028D1C_CB_COLOR3_SLICE, 0, 0}, + {R_028D20_CB_COLOR3_VIEW, 0, 0}, + {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0}, + {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028D2C_CB_COLOR3_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D54_CB_COLOR4_PITCH, 0, 0}, + {R_028D58_CB_COLOR4_SLICE, 0, 0}, + {R_028D5C_CB_COLOR4_VIEW, 0, 0}, + {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0}, + {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028D68_CB_COLOR4_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D90_CB_COLOR5_PITCH, 0, 0}, + {R_028D94_CB_COLOR5_SLICE, 0, 0}, + {R_028D98_CB_COLOR5_VIEW, 0, 0}, + {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0}, + {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028DA4_CB_COLOR5_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0}, + {R_028DCC_CB_COLOR6_PITCH, 0, 0}, + {R_028DD0_CB_COLOR6_SLICE, 0, 0}, + {R_028DD4_CB_COLOR6_VIEW, 0, 0}, + {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0}, + {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028DE0_CB_COLOR6_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E08_CB_COLOR7_PITCH, 0, 0}, + {R_028E0C_CB_COLOR7_SLICE, 0, 0}, + {R_028E10_CB_COLOR7_VIEW, 0, 0}, + {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E1C_CB_COLOR7_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E44_CB_COLOR8_PITCH, 0, 0}, + {R_028E48_CB_COLOR8_SLICE, 0, 0}, + {R_028E4C_CB_COLOR8_VIEW, 0, 0}, + {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E58_CB_COLOR8_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E60_CB_COLOR9_PITCH, 0, 0}, + {R_028E64_CB_COLOR9_SLICE, 0, 0}, + {R_028E68_CB_COLOR9_VIEW, 0, 0}, + {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E74_CB_COLOR9_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E7C_CB_COLOR10_PITCH, 0, 0}, + {R_028E80_CB_COLOR10_SLICE, 0, 0}, + {R_028E84_CB_COLOR10_VIEW, 0, 0}, + {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E90_CB_COLOR10_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E98_CB_COLOR11_PITCH, 0, 0}, + {R_028E9C_CB_COLOR11_SLICE, 0, 0}, + {R_028EA0_CB_COLOR11_VIEW, 0, 0}, + {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0}, + {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028EAC_CB_COLOR11_DIM, 0, 0}, }; static const struct r600_reg cayman_context_reg_list[] = { - {R_028000_DB_RENDER_CONTROL, 0, 0, 0}, - {R_028004_DB_COUNT_CONTROL, 0, 0, 0}, - {R_028008_DB_DEPTH_VIEW, 0, 0, 0}, - {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, - {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028044_DB_STENCIL_INFO, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028058_DB_DEPTH_SIZE, 0, 0, 0}, - {R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, - {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0, 0}, - {R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {R_028350_SX_MISC, 0, 0, 0}, - {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {R_028414_CB_BLEND_RED, 0, 0, 0}, - {R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {R_028438_SX_ALPHA_REF, 0, 0, 0}, - {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, - {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, - {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, - {R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, - {R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, - {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, - {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, - {R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, - {R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, - {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, - {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, - {R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, - {R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, - {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, - {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, - {R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, - {R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, - {R_028600_PA_CL_UCP4_Y, 0, 0, 0}, - {R_028604_PA_CL_UCP4_Z, 0, 0, 0}, - {R_028608_PA_CL_UCP4_W, 0, 0, 0}, - {R_02860C_PA_CL_UCP5_X, 0, 0, 0}, - {R_028610_PA_CL_UCP5_Y, 0, 0, 0}, - {R_028614_PA_CL_UCP5_Z, 0, 0, 0}, - {R_028618_PA_CL_UCP5_W, 0, 0, 0}, - {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, - {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, - {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, - {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, - {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, - {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, - {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, - {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, - {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, - {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, - {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, - {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, - {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, - {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {CM_R_028804_DB_EQAA, 0, 0, 0}, - {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, - {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0, 0}, - {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, - {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0, 0}, - {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, - {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0, 0}, - {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {CM_R_0288E8_SQ_LDS_ALLOC, 0, 0, 0}, - {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, - {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, - {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, - {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, - {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {R_028A0C_PA_SC_LINE_STIPPLE, 0 ,0, 0}, - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {R_028A40_VGT_GS_MODE, 0, 0, 0}, - {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, - {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, - {CM_R_028AA8_IA_MULTI_VGT_PARAM, 0, 0, 0}, - {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, - {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, - {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, - {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, - {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, - {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, - {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, - {CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0, 0, 0}, - {CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0, 0, 0}, - {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0, 0}, - {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0, 0}, - {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0, 0}, - {CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0, 0}, - {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0, 0}, - {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0, 0}, - {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0, 0}, - {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0, 0}, - {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0, 0}, - {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0, 0}, - {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0, 0}, - {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0, 0}, - {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0, 0}, - {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0, 0}, - {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0, 0}, - {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0, 0}, - {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0, 0}, - {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0, 0}, - {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0, 0}, - {CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0, 0}, - {CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, - {R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, - {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, - {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028C78_CB_COLOR0_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, - {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, - {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, - {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, - {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, - {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, - {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, - {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, - {R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, - {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, - {R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, - {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, - {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028D68_CB_COLOR4_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, - {R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, - {R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, - {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, - {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, - {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, - {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, - {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, - {R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, - {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, - {R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, - {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, - {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E58_CB_COLOR8_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, - {R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, - {R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, - {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E74_CB_COLOR9_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, - {R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, - {R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, - {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028E90_CB_COLOR10_DIM, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, - {R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, - {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, - {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, - {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, + {R_028000_DB_RENDER_CONTROL, 0, 0}, + {R_028004_DB_COUNT_CONTROL, 0, 0}, + {R_028008_DB_DEPTH_VIEW, 0, 0}, + {R_02800C_DB_RENDER_OVERRIDE, 0, 0}, + {R_028010_DB_RENDER_OVERRIDE2, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028044_DB_STENCIL_INFO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028058_DB_DEPTH_SIZE, 0, 0}, + {R_02805C_DB_DEPTH_SLICE, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0}, + {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0}, + {R_02823C_CB_SHADER_MASK, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0}, + {R_028350_SX_MISC, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0}, + {R_0285BC_PA_CL_UCP0_X, 0, 0}, + {R_0285C0_PA_CL_UCP0_Y, 0, 0}, + {R_0285C4_PA_CL_UCP0_Z, 0, 0}, + {R_0285C8_PA_CL_UCP0_W, 0, 0}, + {R_0285CC_PA_CL_UCP1_X, 0, 0}, + {R_0285D0_PA_CL_UCP1_Y, 0, 0}, + {R_0285D4_PA_CL_UCP1_Z, 0, 0}, + {R_0285D8_PA_CL_UCP1_W, 0, 0}, + {R_0285DC_PA_CL_UCP2_X, 0, 0}, + {R_0285E0_PA_CL_UCP2_Y, 0, 0}, + {R_0285E4_PA_CL_UCP2_Z, 0, 0}, + {R_0285E8_PA_CL_UCP2_W, 0, 0}, + {R_0285EC_PA_CL_UCP3_X, 0, 0}, + {R_0285F0_PA_CL_UCP3_Y, 0, 0}, + {R_0285F4_PA_CL_UCP3_Z, 0, 0}, + {R_0285F8_PA_CL_UCP3_W, 0, 0}, + {R_0285FC_PA_CL_UCP4_X, 0, 0}, + {R_028600_PA_CL_UCP4_Y, 0, 0}, + {R_028604_PA_CL_UCP4_Z, 0, 0}, + {R_028608_PA_CL_UCP4_W, 0, 0}, + {R_02860C_PA_CL_UCP5_X, 0, 0}, + {R_028610_PA_CL_UCP5_Y, 0, 0}, + {R_028614_PA_CL_UCP5_Z, 0, 0}, + {R_028618_PA_CL_UCP5_W, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_1, 0, 0}, + {R_028624_SPI_VS_OUT_ID_2, 0, 0}, + {R_028628_SPI_VS_OUT_ID_3, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_4, 0, 0}, + {R_028630_SPI_VS_OUT_ID_5, 0, 0}, + {R_028634_SPI_VS_OUT_ID_6, 0, 0}, + {R_028638_SPI_VS_OUT_ID_7, 0, 0}, + {R_02863C_SPI_VS_OUT_ID_8, 0, 0}, + {R_028640_SPI_VS_OUT_ID_9, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0}, + {R_0286E0_SPI_BARYC_CNTL, 0, 0}, + {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0}, + {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0}, + {CM_R_028804_DB_EQAA, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0}, + {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, + {R_028844_SQ_PGM_RESOURCES_PS, 0, 0}, + {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0}, + {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0}, + {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0}, + {R_028860_SQ_PGM_RESOURCES_VS, 0, 0}, + {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0}, + {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0}, + {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0}, + {CM_R_0288E8_SQ_LDS_ALLOC, 0, 0}, + {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0}, + {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0}, + {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0}, + {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0}, + {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0}, + {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0}, + {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0}, + {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0}, + {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0}, + {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0}, + {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0}, + {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0}, + {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0}, + {R_028A48_PA_SC_MODE_CNTL_0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0}, + {CM_R_028AA8_IA_MULTI_VGT_PARAM, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0}, + {R_028ABC_DB_HTILE_SURFACE, 0, 0}, + {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0}, + {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0}, + {R_028AC8_DB_PRELOAD_CONTROL, 0, 0}, + {R_028B54_VGT_SHADER_STAGES_EN, 0, 0}, + {R_028B70_DB_ALPHA_TO_MASK, 0, 0}, + {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0}, + {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0}, + {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0}, + {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0}, + {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0}, + {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0}, + {R_028B94_VGT_STRMOUT_CONFIG, 0, 0}, + {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0}, + {CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0, 0}, + {CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0, 0}, + {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0}, + {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0}, + {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0}, + {CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0}, + {CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0}, + {CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0}, + {CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0}, + {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0}, + {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0}, + {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0}, + {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0}, + {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0}, + {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0}, + {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0}, + {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0}, + {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0}, + {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0}, + {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0}, + {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0}, + {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0}, + {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0}, + {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0}, + {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0}, + {CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0}, + {CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0}, + {R_028C64_CB_COLOR0_PITCH, 0, 0}, + {R_028C68_CB_COLOR0_SLICE, 0, 0}, + {R_028C6C_CB_COLOR0_VIEW, 0, 0}, + {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0}, + {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028C78_CB_COLOR0_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0}, + {R_028CA0_CB_COLOR1_PITCH, 0, 0}, + {R_028CA4_CB_COLOR1_SLICE, 0, 0}, + {R_028CA8_CB_COLOR1_VIEW, 0, 0}, + {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0}, + {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028CB4_CB_COLOR1_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0}, + {R_028CDC_CB_COLOR2_PITCH, 0, 0}, + {R_028CE0_CB_COLOR2_SLICE, 0, 0}, + {R_028CE4_CB_COLOR2_VIEW, 0, 0}, + {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0}, + {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028CF0_CB_COLOR2_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D18_CB_COLOR3_PITCH, 0, 0}, + {R_028D1C_CB_COLOR3_SLICE, 0, 0}, + {R_028D20_CB_COLOR3_VIEW, 0, 0}, + {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0}, + {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028D2C_CB_COLOR3_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D54_CB_COLOR4_PITCH, 0, 0}, + {R_028D58_CB_COLOR4_SLICE, 0, 0}, + {R_028D5C_CB_COLOR4_VIEW, 0, 0}, + {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0}, + {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028D68_CB_COLOR4_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0}, + {R_028D90_CB_COLOR5_PITCH, 0, 0}, + {R_028D94_CB_COLOR5_SLICE, 0, 0}, + {R_028D98_CB_COLOR5_VIEW, 0, 0}, + {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0}, + {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028DA4_CB_COLOR5_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0}, + {R_028DCC_CB_COLOR6_PITCH, 0, 0}, + {R_028DD0_CB_COLOR6_SLICE, 0, 0}, + {R_028DD4_CB_COLOR6_VIEW, 0, 0}, + {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0}, + {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028DE0_CB_COLOR6_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E08_CB_COLOR7_PITCH, 0, 0}, + {R_028E0C_CB_COLOR7_SLICE, 0, 0}, + {R_028E10_CB_COLOR7_VIEW, 0, 0}, + {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E1C_CB_COLOR7_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E44_CB_COLOR8_PITCH, 0, 0}, + {R_028E48_CB_COLOR8_SLICE, 0, 0}, + {R_028E4C_CB_COLOR8_VIEW, 0, 0}, + {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E58_CB_COLOR8_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E60_CB_COLOR9_PITCH, 0, 0}, + {R_028E64_CB_COLOR9_SLICE, 0, 0}, + {R_028E68_CB_COLOR9_VIEW, 0, 0}, + {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E74_CB_COLOR9_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E7C_CB_COLOR10_PITCH, 0, 0}, + {R_028E80_CB_COLOR10_SLICE, 0, 0}, + {R_028E84_CB_COLOR10_VIEW, 0, 0}, + {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0}, + {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028E90_CB_COLOR10_DIM, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0}, + {R_028E98_CB_COLOR11_PITCH, 0, 0}, + {R_028E9C_CB_COLOR11_SLICE, 0, 0}, + {R_028EA0_CB_COLOR11_VIEW, 0, 0}, + {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0}, + {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0}, + {R_028EAC_CB_COLOR11_DIM, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) { struct r600_reg r600_shader_resource[] = { - {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0, 0}, - {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0, 0}, - {R_030008_RESOURCE0_WORD2, 0, 0, 0}, - {R_03000C_RESOURCE0_WORD3, 0, 0, 0}, - {R_030010_RESOURCE0_WORD4, 0, 0, 0}, - {R_030014_RESOURCE0_WORD5, 0, 0, 0}, - {R_030018_RESOURCE0_WORD6, 0, 0, 0}, - {R_03001C_RESOURCE0_WORD7, 0, 0, 0}, + {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0}, + {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0}, + {R_030008_RESOURCE0_WORD2, 0, 0}, + {R_03000C_RESOURCE0_WORD3, 0, 0}, + {R_030010_RESOURCE0_WORD4, 0, 0}, + {R_030014_RESOURCE0_WORD5, 0, 0}, + {R_030018_RESOURCE0_WORD6, 0, 0}, + {R_03001C_RESOURCE0_WORD7, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); @@ -850,9 +850,9 @@ static int r600_resource_range_init(struct r600_context *ctx, struct r600_range static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) { struct r600_reg r600_shader_sampler[] = { - {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); @@ -866,11 +866,11 @@ static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id) { struct r600_reg r600_shader_sampler_border[] = { - {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, - {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0}, + {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; @@ -903,7 +903,6 @@ static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset) r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; - r600_loop_consts[i].flush_mask = 0; } return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET); } diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index ba15ac8afec..b7ba0681845 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -266,378 +266,378 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, /* R600/R700 configuration */ static const struct r600_reg r600_config_reg_list[] = { - {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, - {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0}, + {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, + {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, }; static const struct r600_reg r600_ctl_const_list[] = { - {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0}, }; static const struct r600_reg r600_context_reg_list[] = { - {R_028350_SX_MISC, 0, 0, 0}, - {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, - {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, - {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {R_028A40_VGT_GS_MODE, 0, 0, 0}, - {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, - {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, - {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, - {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028060_CB_COLOR0_SIZE, 0, 0, 0}, - {R_028080_CB_COLOR0_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028100_CB_COLOR0_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028064_CB_COLOR1_SIZE, 0, 0, 0}, - {R_028084_CB_COLOR1_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028104_CB_COLOR1_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028068_CB_COLOR2_SIZE, 0, 0, 0}, - {R_028088_CB_COLOR2_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028108_CB_COLOR2_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, - {R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_02810C_CB_COLOR3_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028070_CB_COLOR4_SIZE, 0, 0, 0}, - {R_028090_CB_COLOR4_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028110_CB_COLOR4_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028074_CB_COLOR5_SIZE, 0, 0, 0}, - {R_028094_CB_COLOR5_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028114_CB_COLOR5_MASK, 0, 0, 0}, - {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, - {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_028078_CB_COLOR6_SIZE, 0, 0, 0}, - {R_028098_CB_COLOR6_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_028118_CB_COLOR6_MASK, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, - {R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, - {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, - {R_02811C_CB_COLOR7_MASK, 0, 0, 0}, - {R_028120_CB_CLEAR_RED, 0, 0, 0}, - {R_028124_CB_CLEAR_GREEN, 0, 0, 0}, - {R_028128_CB_CLEAR_BLUE, 0, 0, 0}, - {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, - {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0, 0}, - {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0, 0}, - {R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0, 0}, - {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {R_028414_CB_BLEND_RED, 0, 0, 0}, - {R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {R_028424_CB_FOG_RED, 0, 0, 0}, - {R_028428_CB_FOG_GREEN, 0, 0, 0}, - {R_02842C_CB_FOG_BLUE, 0, 0, 0}, - {R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {R_028438_SX_ALPHA_REF, 0, 0, 0}, - {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, - {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, - {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0}, - {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, - {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {R_028804_CB_BLEND_CONTROL, 0, 0, 0}, - {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, - {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, - {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, - {R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, - {R_028C38_CB_CLRCMP_DST, 0, 0, 0}, - {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, - {R_028C48_PA_SC_AA_MASK, 0, 0, 0}, - {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, - {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, - {R_028000_DB_DEPTH_SIZE, 0, 0, 0}, - {R_028004_DB_DEPTH_VIEW, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, - {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, - {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, - {R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, - {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, - {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, - {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, - {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, - {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {R_028E20_PA_CL_UCP0_X, 0, 0, 0}, - {R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, - {R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, - {R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, - {R_028E30_PA_CL_UCP1_X, 0, 0, 0}, - {R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, - {R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, - {R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, - {R_028E40_PA_CL_UCP2_X, 0, 0, 0}, - {R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, - {R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, - {R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, - {R_028E50_PA_CL_UCP3_X, 0, 0, 0}, - {R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, - {R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, - {R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, - {R_028E60_PA_CL_UCP4_X, 0, 0, 0}, - {R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, - {R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, - {R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, - {R_028E70_PA_CL_UCP5_X, 0, 0, 0}, - {R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, - {R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, - {R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, - {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, - {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, - {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, - {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, - {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, - {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, - {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, - {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, - {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, - {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, - {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, - {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, - {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, - {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, - {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, - {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, - {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, + {R_028350_SX_MISC, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0}, + {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0}, + {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0}, + {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0}, + {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0}, + {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0}, + {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0}, + {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0}, + {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0}, + {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL, 0, 0}, + {R_028AB0_VGT_STRMOUT_EN, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0}, + {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0}, + {R_028060_CB_COLOR0_SIZE, 0, 0}, + {R_028080_CB_COLOR0_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0}, + {R_028100_CB_COLOR0_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0}, + {R_028064_CB_COLOR1_SIZE, 0, 0}, + {R_028084_CB_COLOR1_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0}, + {R_028104_CB_COLOR1_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0}, + {R_028068_CB_COLOR2_SIZE, 0, 0}, + {R_028088_CB_COLOR2_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0}, + {R_028108_CB_COLOR2_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0}, + {R_02806C_CB_COLOR3_SIZE, 0, 0}, + {R_02808C_CB_COLOR3_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0}, + {R_02810C_CB_COLOR3_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0}, + {R_028070_CB_COLOR4_SIZE, 0, 0}, + {R_028090_CB_COLOR4_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0}, + {R_028110_CB_COLOR4_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0}, + {R_028074_CB_COLOR5_SIZE, 0, 0}, + {R_028094_CB_COLOR5_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0}, + {R_028114_CB_COLOR5_MASK, 0, 0}, + {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)}, + {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0}, + {R_028078_CB_COLOR6_SIZE, 0, 0}, + {R_028098_CB_COLOR6_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0}, + {R_028118_CB_COLOR6_MASK, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0}, + {R_02807C_CB_COLOR7_SIZE, 0, 0}, + {R_02809C_CB_COLOR7_VIEW, 0, 0}, + {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0}, + {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0}, + {R_02811C_CB_COLOR7_MASK, 0, 0}, + {R_028120_CB_CLEAR_RED, 0, 0}, + {R_028124_CB_CLEAR_GREEN, 0, 0}, + {R_028128_CB_CLEAR_BLUE, 0, 0}, + {R_02812C_CB_CLEAR_ALPHA, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0}, + {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0}, + {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0}, + {R_02823C_CB_SHADER_MASK, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0}, + {R_028424_CB_FOG_RED, 0, 0}, + {R_028428_CB_FOG_GREEN, 0, 0}, + {R_02842C_CB_FOG_BLUE, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0}, + {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0}, + {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0}, + {R_0287A0_CB_SHADER_CONTROL, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0}, + {R_028804_CB_BLEND_CONTROL, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0}, + {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0}, + {R_028C30_CB_CLRCMP_CONTROL, 0, 0}, + {R_028C34_CB_CLRCMP_SRC, 0, 0}, + {R_028C38_CB_CLRCMP_DST, 0, 0}, + {R_028C3C_CB_CLRCMP_MSK, 0, 0}, + {R_028C48_PA_SC_AA_MASK, 0, 0}, + {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0}, + {R_028D44_DB_ALPHA_TO_MASK, 0, 0}, + {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH}, + {R_028000_DB_DEPTH_SIZE, 0, 0}, + {R_028004_DB_DEPTH_VIEW, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0}, + {R_028D0C_DB_RENDER_CONTROL, 0, 0}, + {R_028D10_DB_RENDER_OVERRIDE, 0, 0}, + {R_028D24_DB_HTILE_SURFACE, 0, 0}, + {R_028D30_DB_PRELOAD_CONTROL, 0, 0}, + {R_028D34_DB_PREFETCH_LIMIT, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0}, + {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0}, + {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0}, + {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0}, + {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0}, + {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0}, + {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0}, + {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0}, + {R_028E20_PA_CL_UCP0_X, 0, 0}, + {R_028E24_PA_CL_UCP0_Y, 0, 0}, + {R_028E28_PA_CL_UCP0_Z, 0, 0}, + {R_028E2C_PA_CL_UCP0_W, 0, 0}, + {R_028E30_PA_CL_UCP1_X, 0, 0}, + {R_028E34_PA_CL_UCP1_Y, 0, 0}, + {R_028E38_PA_CL_UCP1_Z, 0, 0}, + {R_028E3C_PA_CL_UCP1_W, 0, 0}, + {R_028E40_PA_CL_UCP2_X, 0, 0}, + {R_028E44_PA_CL_UCP2_Y, 0, 0}, + {R_028E48_PA_CL_UCP2_Z, 0, 0}, + {R_028E4C_PA_CL_UCP2_W, 0, 0}, + {R_028E50_PA_CL_UCP3_X, 0, 0}, + {R_028E54_PA_CL_UCP3_Y, 0, 0}, + {R_028E58_PA_CL_UCP3_Z, 0, 0}, + {R_028E5C_PA_CL_UCP3_W, 0, 0}, + {R_028E60_PA_CL_UCP4_X, 0, 0}, + {R_028E64_PA_CL_UCP4_Y, 0, 0}, + {R_028E68_PA_CL_UCP4_Z, 0, 0}, + {R_028E6C_PA_CL_UCP4_W, 0, 0}, + {R_028E70_PA_CL_UCP5_X, 0, 0}, + {R_028E74_PA_CL_UCP5_Y, 0, 0}, + {R_028E78_PA_CL_UCP5_Z, 0, 0}, + {R_028E7C_PA_CL_UCP5_W, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0}, + {R_028614_SPI_VS_OUT_ID_0, 0, 0}, + {R_028618_SPI_VS_OUT_ID_1, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_2, 0, 0}, + {R_028620_SPI_VS_OUT_ID_3, 0, 0}, + {R_028624_SPI_VS_OUT_ID_4, 0, 0}, + {R_028628_SPI_VS_OUT_ID_5, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_6, 0, 0}, + {R_028630_SPI_VS_OUT_ID_7, 0, 0}, + {R_028634_SPI_VS_OUT_ID_8, 0, 0}, + {R_028638_SPI_VS_OUT_ID_9, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028868_SQ_PGM_RESOURCES_VS, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0}, + {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0}, + {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0}, + {R_028850_SQ_PGM_RESOURCES_PS, 0, 0}, + {R_028854_SQ_PGM_EXPORTS_PS, 0, 0}, + {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0}, + {R_028A84_VGT_PRIMITIVEID_EN, 0, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0}, + {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0}, + {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ @@ -668,13 +668,13 @@ int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsig static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) { struct r600_reg r600_shader_resource[] = { - {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0, 0}, - {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0, 0}, - {R_038008_RESOURCE0_WORD2, 0, 0, 0}, - {R_03800C_RESOURCE0_WORD3, 0, 0, 0}, - {R_038010_RESOURCE0_WORD4, 0, 0, 0}, - {R_038014_RESOURCE0_WORD5, 0, 0, 0}, - {R_038018_RESOURCE0_WORD6, 0, 0, 0}, + {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0}, + {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0}, + {R_038008_RESOURCE0_WORD2, 0, 0}, + {R_03800C_RESOURCE0_WORD3, 0, 0}, + {R_038010_RESOURCE0_WORD4, 0, 0}, + {R_038014_RESOURCE0_WORD5, 0, 0}, + {R_038018_RESOURCE0_WORD6, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); @@ -685,9 +685,9 @@ static int r600_resource_range_init(struct r600_context *ctx, struct r600_range static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) { struct r600_reg r600_shader_sampler[] = { - {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); @@ -701,10 +701,10 @@ static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset) { struct r600_reg r600_shader_sampler_border[] = { - {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); @@ -724,7 +724,6 @@ static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset) r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; - r600_loop_consts[i].flush_mask = 0; } return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); } diff --git a/src/gallium/drivers/r600/r600_hw_context_priv.h b/src/gallium/drivers/r600/r600_hw_context_priv.h index 55df6e991b7..ed566230982 100644 --- a/src/gallium/drivers/r600/r600_hw_context_priv.h +++ b/src/gallium/drivers/r600/r600_hw_context_priv.h @@ -48,7 +48,6 @@ struct r600_reg { unsigned offset; unsigned flags; unsigned flush_flags; - unsigned flush_mask; }; /* |