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author | Kenneth Graunke <[email protected]> | 2016-01-11 12:25:12 -0800 |
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committer | Kenneth Graunke <[email protected]> | 2016-01-12 12:19:47 -0800 |
commit | 9095847c254be2d55ab188232aa6b84555dbac4e (patch) | |
tree | 9316667c6e3e744a4cae806b47311a967b537b05 /.travis.yml | |
parent | 56fc2986d554b93d16fa1151765a9987bc42e4da (diff) |
i965: Mark TCS URB writes as having side effects.
This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing
reads and writes from being incorrectly scheduled.
Fixes rendering in GFXBench 4.0's tessellation demo.
For some reason, we haven't ever listed URB writes as having
side-effects. This hasn't been a problem because in most stages, we
never read from the URB, and only write to each location once.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93526
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Diffstat (limited to '.travis.yml')
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