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author | Robert Ellison <[email protected]> | 2008-10-30 15:24:23 -0600 |
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committer | Robert Ellison <[email protected]> | 2008-10-30 15:24:52 -0600 |
commit | 711f8a1dd94e2e1e715615d947e03015ef972326 (patch) | |
tree | 4365c6e97f3705b754714702dbbe2cff2ccac53b /.emacs-dirvars | |
parent | 157ddc14183807834068687f02c67b66acf9effa (diff) |
CELL: stencil bug fixes
Two definitive bugs in stenciling were fixed.
The first, reversed registers in the generated Select Bytes (selb)
instruction, caused the stenciling INCR and DECR operations to
fail dramatically, putting new values in where old values were
supposed to be and vice versa.
The second caused stencil tiles to not be read and written from
main memory by the SPUs. A per-spu flag, spu.read_depth, was used
to indicate whether the SPU should be reading depth tiles, and was set
only when depth was enabled. A second flag, spu.read_stencil, was
set when stenciling was enabled, but never referenced.
As stenciling and depth are in the same tiles on the Cell, and there
is no corresponding TAG_WRITE_TILE_STENCIL to complement
TAG_WRITE_TILE_COLOR and TAG_WRITE_TILE_Z, I fixed this by
eliminating the unused "spu.read_stencil", renaming "spu.read_depth"
to "spu.read_depth_stencil", and setting it if either stenciling or
depth is enabled.
I also added an optimization to the fragment ops generation code,
that avoids calculating stencil values and/or stencil writemask
when the stencil operations are all KEEP.
Diffstat (limited to '.emacs-dirvars')
0 files changed, 0 insertions, 0 deletions