1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
/**
* Lightweight wrappers for SSE2 intrinsics for 32-bit operations
*/
#ifndef BOTAN_SIMD_SSE_H__
#define BOTAN_SIMD_SSE_H__
#include <botan/types.h>
#include <emmintrin.h>
namespace Botan {
class SIMD_SSE2
{
public:
SIMD_SSE2(const u32bit B[4])
{
reg = _mm_loadu_si128((const __m128i*)B);
}
SIMD_SSE2(u32bit B0, u32bit B1, u32bit B2, u32bit B3)
{
reg = _mm_set_epi32(B0, B1, B2, B3);
}
SIMD_SSE2(u32bit B)
{
reg = _mm_set1_epi32(B);
}
static SIMD_SSE2 load_le(const void* in)
{
return _mm_loadu_si128((const __m128i*)in);
}
static SIMD_SSE2 load_be(const void* in)
{
return SIMD_SSE2(_mm_loadu_si128((const __m128i*)in)).bswap();
}
void store_le(byte out[]) const
{
_mm_storeu_si128((__m128i*)out, reg);
}
void store_be(byte out[]) const
{
bswap().store_le(out);
}
void rotate_left(u32bit rot)
{
reg = _mm_or_si128(_mm_slli_epi32(reg, rot),
_mm_srli_epi32(reg, 32-rot));
}
void rotate_right(u32bit rot)
{
reg = _mm_or_si128(_mm_srli_epi32(reg, rot),
_mm_slli_epi32(reg, 32-rot));
}
void operator+=(const SIMD_SSE2& other)
{
reg = _mm_add_epi32(reg, other.reg);
}
SIMD_SSE2 operator+(const SIMD_SSE2& other) const
{
return _mm_add_epi32(reg, other.reg);
}
void operator^=(const SIMD_SSE2& other)
{
reg = _mm_xor_si128(reg, other.reg);
}
SIMD_SSE2 operator^(const SIMD_SSE2& other) const
{
return _mm_xor_si128(reg, other.reg);
}
void operator|=(const SIMD_SSE2& other)
{
reg = _mm_or_si128(reg, other.reg);
}
void operator&=(const SIMD_SSE2& other)
{
reg = _mm_and_si128(reg, other.reg);
}
SIMD_SSE2 operator<<(u32bit shift) const
{
return _mm_slli_epi32(reg, shift);
}
SIMD_SSE2 operator>>(u32bit shift) const
{
return _mm_srli_epi32(reg, shift);
}
SIMD_SSE2 operator~() const
{
static const __m128i all_ones = _mm_set1_epi32(0xFFFFFFFF);
return _mm_xor_si128(reg, all_ones);
}
static void transpose(SIMD_SSE2& B0, SIMD_SSE2& B1,
SIMD_SSE2& B2, SIMD_SSE2& B3)
{
__m128i T0 = _mm_unpacklo_epi32(B0.reg, B1.reg);
__m128i T1 = _mm_unpacklo_epi32(B2.reg, B3.reg);
__m128i T2 = _mm_unpackhi_epi32(B0.reg, B1.reg);
__m128i T3 = _mm_unpackhi_epi32(B2.reg, B3.reg);
B0.reg = _mm_unpacklo_epi64(T0, T1);
B1.reg = _mm_unpackhi_epi64(T0, T1);
B2.reg = _mm_unpacklo_epi64(T2, T3);
B3.reg = _mm_unpackhi_epi64(T2, T3);
}
private:
SIMD_SSE2(__m128i in) { reg = in; }
SIMD_SSE2 bswap() const
{
__m128i T = reg;
T = _mm_shufflehi_epi16(T, _MM_SHUFFLE(2, 3, 0, 1));
T = _mm_shufflelo_epi16(T, _MM_SHUFFLE(2, 3, 0, 1));
return _mm_or_si128(_mm_srli_epi16(T, 8),
_mm_slli_epi16(T, 8));
}
__m128i reg;
};
}
#endif
|
