From 78465d7229c14478b81ecf56fad69a3b598a7415 Mon Sep 17 00:00:00 2001
From: lloyd <lloyd@randombit.net>
Date: Mon, 28 Jun 2010 16:05:24 +0000
Subject: Simplify feature checks

---
 src/utils/cpuid.h | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

(limited to 'src/utils')

diff --git a/src/utils/cpuid.h b/src/utils/cpuid.h
index e0ccee515..a6a278a6e 100644
--- a/src/utils/cpuid.h
+++ b/src/utils/cpuid.h
@@ -27,49 +27,54 @@ class BOTAN_DLL CPUID
       * Check if the processor supports RDTSC
       */
       static bool has_rdtsc()
-         { return ((x86_processor_flags() >> CPUID_RDTSC_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_RDTSC_BIT); }
 
       /**
       * Check if the processor supports SSE2
       */
       static bool has_sse2()
-         { return ((x86_processor_flags() >> CPUID_SSE2_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_SSE2_BIT); }
 
       /**
       * Check if the processor supports SSSE3
       */
       static bool has_ssse3()
-         { return ((x86_processor_flags() >> CPUID_SSSE3_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_SSSE3_BIT); }
 
       /**
       * Check if the processor supports SSE4.1
       */
       static bool has_sse41()
-         { return ((x86_processor_flags() >> CPUID_SSE41_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_SSE41_BIT); }
 
       /**
       * Check if the processor supports SSE4.2
       */
       static bool has_sse42()
-         { return ((x86_processor_flags() >> CPUID_SSE42_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_SSE42_BIT); }
 
       /**
       * Check if the processor supports extended AVX vector instructions
       */
       static bool has_avx()
-         { return ((x86_processor_flags() >> CPUID_AVX_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_AVX_BIT); }
 
       /**
       * Check if the processor supports Intel's AES instructions
       */
       static bool has_aes_intel()
-         { return ((x86_processor_flags() >> CPUID_INTEL_AES_BIT) & 1); }
+         { return x86_processor_flags_has(CPUID_INTEL_AES_BIT); }
 
       /**
       * Check if the processor supports AltiVec/VMX
       */
       static bool has_altivec();
    private:
+      static bool x86_processor_flags_has(u64bit bit)
+         {
+         return ((x86_processor_flags() >> bit) & 1);
+         }
+
       enum CPUID_bits {
          CPUID_RDTSC_BIT = 4,
          CPUID_SSE2_BIT = 26,
-- 
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