| Commit message (Collapse) | Author | Age | Files | Lines |
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than OpenSSL... that's a problem for another branch though).
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Remove support for (unused) modset settings.
Move tss, fpe, cryptobox, and aont to new dir constructs
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containers (specifically vector).
Rename is_empty to empty
Remove has_items
Rename create to resize
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build magic, name them asm_macr_ARCH.h. Change all including files accordingly.
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2 is not in the primes table). Also ensure that a >= b; this guarantees
that log_a(b) is <= 1 and thus only 3 rounds (instead of 8 used before)
is sufficient.
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586495311cff277e7a24b4116c987b79036d94e6)
to branch 'net.randombit.botan.fpe' (head c6e8324b12e509ac1303078d5e716f08c53acff5)
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0cb3295ee48403828c652064fbf72ddb6edbe13c)
to branch 'net.randombit.botan.fpe' (head 954d50f368db4be7d98c5c32c474bc54ec5ea7f3)
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Format-Preserving Encryption (http://eprint.iacr.org/2009/251). This
doesn't implement the rank functions which are necessary for the actual
format-preserving part, though that would be nice to add to the example.
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the Alpha EV67 and MIPS R10000.
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the same as an UltraSPARC for optimization purposes.
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x64 as another arch alias since some people seem to use it.
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to give a 3-7% speed improvement on Core2 with GCC.
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an extra 4 words at the end of EK for writing (unused) values.
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Currently requires SSE4.1 for _mm_extract_epi32 for the key schedule, it
would be nice to remove this dependency, though all currently known/scheduled
chips with AES-NI (Intel Westmere and Sandy Bridge, and AMD Bulldozer) are
supposed to include SSE 4.1 so this is not a huge problem.
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which is currently just a stub returning false.
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No noticable change under the simulator (no surprises there), but should help
a lot with pipelining on real hardware.
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tests under Intel's emulator.
Document and enable in the engine.
Merge both versions to aes_intel.cpp - some shared code and much similiar
structure which might be sharable via macros.
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testing with Intel's emulator shows all green.
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virtual-ness not needed, and was overriding/overloading by argument which
doesn't actually work in C++ and only happened to work because it was only
ever used with the version implemented in that same class. ICC was warning,
too. Make non-virtual.
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credits.txt and thanks.txt. Remove some various bits of formatting weirdness.
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included elsewhere and my preference is for the only emails to be in
credits.txt since emails change more often than names and I'd prefer them
not to be constantly either wrong or needing updates.
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the user to specify the hash function to use, instead of always using SHA-1.
This was a sensible default a few years ago, when there wasn't a ~2^60 attack
on SHA-1 and support for SHA-2 was pretty much nil, but using something else
makes a lot more sense these days.
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the AES and PCLMUL instructions. Oddness. For the time being, compile
Nehalem and Westmere as Core2 + extras, probably close enough.
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on a particular ISA extension rather than a list of CPUs. Much
easier to edit and audit, too. Add markers on the AES-NI code and
SHA-1/SSE2. Serpent and XTEA don't need it because they are
generic and only depend on simd_32 which will silenty swap out a
scalar version if SSE2/AltiVec isn't enabled (since it turns out
on supersclar processors just doing 4 blocks in parallel can be a
win even in GPRs).
Add pentium3 to the list of CPUs with rdtsc, was missing. Odd!
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From looking at how key gen works in particular, it seems easiest to provide
only AES-128, AES-192, and AES-256 and not a general AES class that can
accept any key length. This also has the bonus of allowing full loop unrolling
which may be a win (how much so will depend on the latency/throughput of
the AES instructions which is currently unknown).
No block interleaving, though of course it works very nicely here, simply
due to the desire to keep things simple until what is currently here can
actually be tested. (Intel has an emulator that is supposed to work but
just crashes on my machine...)
I'm not entirely sure if byte swapping is required. Intel has a white paper
out that suggests it isn't (and really it would have been stupid of them to
not build this into the aes instructions), but who knows. If it turns
out to be necessary there is a pretty fast bswap instruction for SSE anyway.
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providing it. Also stubs in the engine for VIA's AES instructions, but
needs CPUID checking also.
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ignores this unless it can detect (or is asked to use) a specific model;
otherwise it compiles for the baseline ISA. Remove the default_submodel
entries in the arch files.
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ISA extensions (say, Intel's AES-NI, for instance) so change everything
to reflect that.
Also rename some of the amd64 models, and add entries for k10, nehalem,
and westmere processors.
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Rename BOTAN_UNALIGNED_LOADSTOR_OK to BOTAN_UNALIGNED_MEMORY_ACCESS_OK
which is somewhat more clear as to the point.
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SSE2, SSSE3, NEON, and AltiVec.
Add entries for Intel Atom, POWER6 and POWER7, and the Cortex A8 and A9.
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