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* ABI for Aarch64 cryptoJack Lloyd2018-01-121-0/+1
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* Recognize armv7-a [ci skip]Jack Lloyd2018-01-091-0/+1
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* Remove CPU specific optimization flagsJack Lloyd2018-01-0818-295/+11
| | | | | | | These are best left to the user to set via CXXFLAGS or --cc-abi-flags Add override if arch ends in in {eb, el, be, le} to set the endian. Avoids an extra file for ppc64le.
* Rename SSE4.x names to avoid underscoresJack Lloyd2017-12-112-4/+4
| | | | | | This breaks how we determine the ISA flags for amalgamation files. The code for doing that is kind of a hack but I don't want to mess with it right now, easier to just rename the ISA internally.
* Rename the SSE4 ISA extensionsJack Lloyd2017-12-112-4/+4
| | | | Simplifies macro generation
* Remove unaligned mem checkJack Lloyd2017-12-026-8/+0
| | | | | | | | | | This previously enabled doing something unsafe (misaligned reads), but it turns out even on hardware that supports this, it is not safe to do because the compiler may do something unfortunate. Now memcpy is used, which is safe on any platform. Should provide a noticable speedup for ARM and PPC64, which previously used the byte-at-a-time fallback code.
* Add some additional CPU aliases for x86-64Jack Lloyd2017-10-121-5/+8
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* Script the Windows CI buildJack Lloyd2017-09-081-0/+1
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* Sort isa_extensions lists [ci skip]Simon Warta2017-09-024-14/+11
| | | | this removes the duplicate "sha" in x86_64
* Add support for LLVM bitcode targetJack Lloyd2017-08-301-0/+1
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* Add support for Intel SHA-1/SHA-2 instructionsJack Lloyd2017-05-191-0/+1
| | | | Based on GH #807 and #808
* Add ppc64le (POWER8 little endian) as supported cpuGustavo Serra Scalet2017-03-201-0/+22
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* Add support for NEON in SIMD_4x32Jack Lloyd2017-01-291-0/+4
| | | | Tested on qemu-aarch64
* Fix configure.py error when compiler doesn't support desired ISA flagsJack Lloyd2017-01-221-1/+0
| | | | | | | | | | | | | Seen with rarely tested compilers (Sun Studio, Intel, ...) that we are missing info for. Previously this led to a hard error which is pointless. Instead just disable the relevant module and warn the user that something was disabled, if they want to go look into why. Remove bogus clmul entry in x86_64 - actually we lump both AES and CLMUL flags under the same ISA ("aesni") since all known CPUs support either both or neither. Caught by new configure warning. Add Sun Studio ISA flags from GH #846
* add support for Intel RdSeedDaniel Neus2015-12-182-0/+2
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* Initial support for 64 bit ARMDaniel Seither2015-10-132-1/+13
| | | | | | | | | | | | | | | This adds support for 64 bit ARM cores as used in many high-end phones such as all iPhones beginning with the 5s. While these newer phones still run 32 bit ARM code, Apple doesn't allow apps to be submitted to the app store if they don't provide a 64 bit build. This commit adds a new arm64 arch and renames arm to arm32 to stay consistent with the other architectures. The name arm can still be used for configuring because it has been added as an alias for arm32. Additionally, the one piece of ARM inline assembly that can be found in Botan doesn't work on 64 bit ARM, so I use the solution that has been proposed in #180: Use __builtin_bswap32 instead of inline assembly.
* Add evbarm as platform alias for NetBSD. GH#81joerg2015-04-271-0/+1
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* Add power8 targetlloyd2015-02-271-0/+1
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* Split amalagamation into ISA specific objectslloyd2015-02-221-1/+0
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* Set -m flags for rdrand.cpp. Update compiler ISA flagslloyd2013-12-232-2/+8
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* Add a generic 64x64->128 multiplication op.lloyd2013-07-307-0/+9
| | | | | | | Use it to merge mp_msvc64 (was using MSVC _umul128 intrinsic) and mp_asm64 (was using inline asm) into mp_word64, which calls the new mul64x64_128 function. That function wraps any available compiler intrinsics or CPU instructions.
* Always include modules requiring ISA extensions as long as thelloyd2013-04-175-26/+33
| | | | | | | | | | | compiler and target platform might support it. For instance the AES SSSE3 code is now always in any x86 build, with just that specific file being compiled with -mssse3. Since we'll only call that code if cpuid confirms it works at runtime, we don't have portability issues, and it can be safely included in generic builds (eg for distributions). Tweak how machine specific compiler flags are generated to be a bit easier to maintain.
* Alias mips64el to mips64, from Brad Smithlloyd2013-03-211-0/+4
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* Add a --chost option to configure that takes a GNU style triplet.lloyd2012-08-311-2/+3
| | | | | | Add a couple aliases so the GNU canonical names are understood by us. Add an Ivy Bridge entry, match it up with the new GCC -march flag
* Add model name for Sandy Bridge. Use -march=corei7 with GCC and Clanglloyd2011-11-181-3/+4
| | | | as they seem to understand it as of GCC 4.6 and Clang 2.9.
* Add specialization for i486 that uses -mtune=generic, as Debianlloyd2011-05-131-1/+0
| | | | | | | | | | | | invokes the build with --cpu=i486 on x86-32. Add -momit-leaf-frame-pointer to x86 specializations. Use -march=atom for atom32 as well. Use -mcpu=cell for Cell PPU - it's not documented, but GCC 4.6 has it. Remove ancient/untested rs64a support from ppc64
* Renaming the ppc target to ppc32 prevented -mcpu flags from being setlloyd2011-05-121-0/+2
| | | | | | | by GCC. Add Niagra targets for sparc, and extend/fix the Sun Studio flags for SPARC64.
* Add support for targetting the PowerPCSPE (an embedded PPC with anlloyd2011-05-122-5/+13
| | | | | experimental Debian port), and add aliases for ARM to match the Debian architectures.
* Make different targets for 32 and 64 bit Atom processors, since mostlloyd2011-05-092-5/+6
| | | | consumer/desktop level Atoms are actually 32 bit.
* Tweak settings for SuperH setup, based on Debian bug 594159. Since aslloyd2011-05-022-7/+5
| | | | | far as I know this is the first and only real use, or even test, of botan on the SH, I'll let them pick the names and flags...
* Default sun4u to sparc32-v9 rather than sparc64lloyd2011-04-292-4/+2
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* Rename all references of ia32 to x86-32 and amd64 to x86-64.lloyd2011-04-222-1/+2
| | | | | | Back the reported version from 1.10.0 to 1.9.17 for the time being. Still on the fence if this will be 1.10.0 or another release candidate instead.
* Enable unix_procs for FreeBSD. It was disabled in 2006 to worklloyd2011-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | around a bug in FreeBSD 6.1, which is long EOL. If we can't figure out the CPU in configure.py, if running verbosely dump the entire list of CPUs we know about. Some doc cleanups. Rename the 'beos' target to 'haiku', since testing shows that botan can't compile under the old BeOS GCC 2.95 anyway. Remove the call to idle_time in the stats entropy source - it causes a crash on Haiku R1-alpha2 somewhere inside a system DLL. I didn't bother debugging it beyond looking at the backtrace. Add a 'bepc' alias for i386 as that is what Haiku reports its processor as. Fix the install dirs to match Haiku R1, though apparently they will change in R2 anyway when they add package management. Enable use of gmtime_r on Haiku.
* One minor fix for QNX 6.4.1 (Python identifies CPU as 'x86pc'), andlloyd2011-04-151-0/+1
| | | | | add support for features that it has that apparently the last version I tested did not, including dynamic loading.
* Assume ARMs are little-endian by default; big-endian ARM seems to be a rarity.lloyd2011-03-141-0/+4
| | | | | | GCC 4.3 on ARM converts __builtin_bswap32 into a jump into libgcc rather than 4 simple instructions, so write it out using inline asm instead.
* Somewhat improved ARM support/autodetectionlloyd2011-03-091-17/+26
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* Alias sun4u to sparc64. This will break for the many people who arelloyd2010-12-151-0/+4
| | | | | | | running 32 bit userspaces on sun4u machines, but it's often difficult to tell what the compiler does/does not support in that respect, and this will work for people who are using 64 bit userspace which I _think_ is more common now. I hope.
* Add support for Atom processors.lloyd2010-08-221-0/+1
| | | | | | | Fix a bug that would cause a harmless but bogus macro to be generated in build.h if you used --enable-sse2 Add --enable-movbe to turn on a macro marking movbe as available
* Identify a i7-860 as Nehalemlloyd2010-08-081-0/+1
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* Fix problem that prevented AES-NI code from getting loaded in at leastlloyd2010-06-111-1/+3
| | | | | | | some cases. Add a westmere alias for "Core i5 CPU M 520", which is what uname (and thus, platform.processor()) returns on my laptop. Mostly for my benefit of course.
* New macro TARGET_CPU_IS_XXX_FAMILY for XXX = X86, PPC, SPARC, undefinedlloyd2009-12-296-0/+13
| | | | elsewhere currently.
* Rename the UltraSPARC submodels; remove UltraSPARC II since it is functionallylloyd2009-11-111-6/+4
| | | | the same as an UltraSPARC for optimization purposes.
* Make em64t just an alias for amd64; add nocona as a submodel. Also addlloyd2009-11-111-1/+3
| | | | x64 as another arch alias since some people seem to use it.
* Add a new need_isa marker for info.txt that lets a module dependlloyd2009-11-061-1/+1
| | | | | | | | | | | | on a particular ISA extension rather than a list of CPUs. Much easier to edit and audit, too. Add markers on the AES-NI code and SHA-1/SSE2. Serpent and XTEA don't need it because they are generic and only depend on simd_32 which will silenty swap out a scalar version if SSE2/AltiVec isn't enabled (since it turns out on supersclar processors just doing 4 blocks in parallel can be a win even in GPRs). Add pentium3 to the list of CPUs with rdtsc, was missing. Odd!
* The default_submodel option was used by configure.pl but configure.pylloyd2009-11-0616-37/+7
| | | | | | ignores this unless it can detect (or is asked to use) a specific model; otherwise it compiles for the baseline ISA. Remove the default_submodel entries in the arch files.
* The code for handling SIMD ISA extensions actually works fine for generallloyd2009-11-065-15/+21
| | | | | | | | ISA extensions (say, Intel's AES-NI, for instance) so change everything to reflect that. Also rename some of the amd64 models, and add entries for k10, nehalem, and westmere processors.
* Generate SIMD macro flags for build.h from data in build-data/arch forlloyd2009-11-065-0/+27
| | | | | | SSE2, SSSE3, NEON, and AltiVec. Add entries for Intel Atom, POWER6 and POWER7, and the Cortex A8 and A9.
* Remove the 'realname' attribute on all modules and cc/cpu/os info files.lloyd2009-10-2916-33/+0
| | | | | Pretty much useless and unused, except for listing the module names in build.h and the short versions totally suffice for that.
* propagate from branch 'net.randombit.botan.1_8' (head ↵lloyd2009-10-284-0/+12
|\ | | | | | | | | | | 3158f8272a3582dd44dfb771665eb71f7d005339) to branch 'net.randombit.botan' (head bf629b13dd132b263e76a72b7eca0f7e4ab19aac)
| * propagate from branch 'net.randombit.botan.1_8' (head ↵lloyd2009-10-134-0/+12
| |\ | | | | | | | | | | | | | | | c5ae189464f6ef16e3ce73ea7c563412460d76a3) to branch 'net.randombit.botan' (head e2b95b6ad31c7539cf9ac0ebddb1d80bf63b5b21)
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