| Commit message (Collapse) | Author | Age | Files | Lines |
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an extra 4 words at the end of EK for writing (unused) values.
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Currently requires SSE4.1 for _mm_extract_epi32 for the key schedule, it
would be nice to remove this dependency, though all currently known/scheduled
chips with AES-NI (Intel Westmere and Sandy Bridge, and AMD Bulldozer) are
supposed to include SSE 4.1 so this is not a huge problem.
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which is currently just a stub returning false.
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No noticable change under the simulator (no surprises there), but should help
a lot with pipelining on real hardware.
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tests under Intel's emulator.
Document and enable in the engine.
Merge both versions to aes_intel.cpp - some shared code and much similiar
structure which might be sharable via macros.
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testing with Intel's emulator shows all green.
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AES-256 blocks, plus a handful remaining in a general AES block.
This is necessary for any implementation which only supports a particular
key size, since otherwise no tests at all will run on that implementation.
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virtual-ness not needed, and was overriding/overloading by argument which
doesn't actually work in C++ and only happened to work because it was only
ever used with the version implemented in that same class. ICC was warning,
too. Make non-virtual.
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credits.txt and thanks.txt. Remove some various bits of formatting weirdness.
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included elsewhere and my preference is for the only emails to be in
credits.txt since emails change more often than names and I'd prefer them
not to be constantly either wrong or needing updates.
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the user to specify the hash function to use, instead of always using SHA-1.
This was a sensible default a few years ago, when there wasn't a ~2^60 attack
on SHA-1 and support for SHA-2 was pretty much nil, but using something else
makes a lot more sense these days.
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the AES and PCLMUL instructions. Oddness. For the time being, compile
Nehalem and Westmere as Core2 + extras, probably close enough.
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on a particular ISA extension rather than a list of CPUs. Much
easier to edit and audit, too. Add markers on the AES-NI code and
SHA-1/SSE2. Serpent and XTEA don't need it because they are
generic and only depend on simd_32 which will silenty swap out a
scalar version if SSE2/AltiVec isn't enabled (since it turns out
on supersclar processors just doing 4 blocks in parallel can be a
win even in GPRs).
Add pentium3 to the list of CPUs with rdtsc, was missing. Odd!
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From looking at how key gen works in particular, it seems easiest to provide
only AES-128, AES-192, and AES-256 and not a general AES class that can
accept any key length. This also has the bonus of allowing full loop unrolling
which may be a win (how much so will depend on the latency/throughput of
the AES instructions which is currently unknown).
No block interleaving, though of course it works very nicely here, simply
due to the desire to keep things simple until what is currently here can
actually be tested. (Intel has an emulator that is supposed to work but
just crashes on my machine...)
I'm not entirely sure if byte swapping is required. Intel has a white paper
out that suggests it isn't (and really it would have been stupid of them to
not build this into the aes instructions), but who knows. If it turns
out to be necessary there is a pretty fast bswap instruction for SSE anyway.
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providing it. Also stubs in the engine for VIA's AES instructions, but
needs CPUID checking also.
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ignores this unless it can detect (or is asked to use) a specific model;
otherwise it compiles for the baseline ISA. Remove the default_submodel
entries in the arch files.
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ISA extensions (say, Intel's AES-NI, for instance) so change everything
to reflect that.
Also rename some of the amd64 models, and add entries for k10, nehalem,
and westmere processors.
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There is no point, as far as I can see, of being able to explicitly disable
a SIMD or other ISA extension, because if you are compiling for that particular
CPU the compiler might well choose to insert CPU-specific instructions anyway.
For instance if one is compiling on a P4 but wants to disable SSE2, the
right thing to do is compile for (say) an i686 which ensures that no P4
instructions will be emitted.
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Rename BOTAN_UNALIGNED_LOADSTOR_OK to BOTAN_UNALIGNED_MEMORY_ACCESS_OK
which is somewhat more clear as to the point.
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SSE2, SSSE3, NEON, and AltiVec.
Add entries for Intel Atom, POWER6 and POWER7, and the Cortex A8 and A9.
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x86 currently. This should be fixed. But it's an improvement over having
to always set it manually, at least.
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6e8c18515725a70923b34118951252723dd4c29a)
to branch 'net.randombit.botan' (head 77ba4ea5a4be36d6d029bcc852b2271edff0d679)
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a101c8c86b755a666c72baf03154230e09e0667e)
to branch 'net.randombit.botan' (head 948905e3872b6f5904686533c6aa87d38ff90a71)
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I'm not totally happy with this - in particular in all cases the size is a
compile time constant - it would be nice to make use of this via tempalate
metaprogramming. Also for matching endian loads, a straight memcpy would
do the work, which would probably be even faster.
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change some of the hash functions to use it as low hanging fruit.
Probably could use further optimization (just unrolls x4 currently), but
merely having it as syntax is good as it allows optimizing many functions
at once (eg using SSE2 to do 4-way byteswaps).
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Document SHA optimizations, AltiVec runtime checking, fixes for cpuid
for both icc and msvc.
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4fd7eb9630271d3c1dfed21987ef864680d4ce7b)
to branch 'net.randombit.botan.general-simd' (head 91df868149cdc4754d340e6103028acc82182609)
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and also make it stylistically much closer to the standard SHA-1 code.
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the code stylistically, etc)
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returns true if they might plausibly work. AltiVec and SSE2 versions call
into CPUID, scalar version always works.
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Relies on mfspr emulation/trapping by the kernel, which works on (at least)
Linux and NetBSD.
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