4 files changed, 22 insertions, 4 deletions
diff --git a/src/utils/simd_32/simd_32.h b/src/utils/simd_32/simd_32.h
index be426efd6..324db1a7d 100644
--- a/src/utils/simd_32/simd_32.h
+++ b/src/utils/simd_32/simd_32.h
@@ -10,8 +10,6 @@
 
 #include <botan/types.h>
 
-//#define BOTAN_TARGET_CPU_HAS_SSE2
-
 #if defined(BOTAN_TARGET_CPU_HAS_SSE2)
 
   #include <botan/simd_sse.h>
diff --git a/src/utils/simd_32/simd_altivec.h b/src/utils/simd_32/simd_altivec.h
index e1aa62002..c6dd8a289 100644
--- a/src/utils/simd_32/simd_altivec.h
+++ b/src/utils/simd_32/simd_altivec.h
@@ -168,6 +168,12 @@ class SIMD_Altivec
          return vec_nor(reg, reg);
          }
 
+      SIMD_Altivec andc(const SIMD_Altivec& other)
+         {
+         // AltiVec does arg1 & ~arg2 rather than SSE's ~arg1 & arg2
+         return vec_andc(other.reg, reg);
+         }
+
       SIMD_Altivec bswap() const
          {
          __vector unsigned char perm = vec_lvsl(0, (u32bit*)0);
diff --git a/src/utils/simd_32/simd_scalar.h b/src/utils/simd_32/simd_scalar.h
index 5fc20b462..398503d33 100644
--- a/src/utils/simd_32/simd_scalar.h
+++ b/src/utils/simd_32/simd_scalar.h
@@ -171,6 +171,15 @@ class SIMD_Scalar
          return SIMD_Scalar(~R0, ~R1, ~R2, ~R3);
          }
 
+      // (~reg) & other
+      SIMD_Scalar andc(const SIMD_Scalar& other)
+         {
+         return SIMD_Scalar(~R0 & other.R0,
+                            ~R1 & other.R1,
+                            ~R2 & other.R2,
+                            ~R3 & other.R3);
+         }
+
       SIMD_Scalar bswap() const
          {
          return SIMD_Scalar(reverse_bytes(R0),
diff --git a/src/utils/simd_32/simd_sse.h b/src/utils/simd_32/simd_sse.h
index c45d8032f..81d8afe75 100644
--- a/src/utils/simd_32/simd_sse.h
+++ b/src/utils/simd_32/simd_sse.h
@@ -117,8 +117,13 @@ class SIMD_SSE2
 
       SIMD_SSE2 operator~() const
          {
-         static const __m128i all_ones = _mm_set1_epi32(0xFFFFFFFF);
-         return _mm_xor_si128(reg, all_ones);
+         return _mm_xor_si128(reg, _mm_set1_epi32(0xFFFFFFFF));
+         }
+
+      // (~reg) & other
+      SIMD_SSE2 andc(const SIMD_SSE2& other)
+         {
+         return _mm_andnot_si128(reg, other.reg);
          }
 
       SIMD_SSE2 bswap() const