diff options
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/simd/simd_altivec/simd_altivec.h | 77 | ||||
| -rw-r--r-- | src/lib/utils/cpuid.cpp | 2 |
2 files changed, 39 insertions, 40 deletions
diff --git a/src/lib/simd/simd_altivec/simd_altivec.h b/src/lib/simd/simd_altivec/simd_altivec.h index f675587bc..133061b97 100644 --- a/src/lib/simd/simd_altivec/simd_altivec.h +++ b/src/lib/simd/simd_altivec/simd_altivec.h @@ -26,17 +26,17 @@ class SIMD_Altivec SIMD_Altivec(const u32bit B[4]) { - reg = (__vector unsigned int){B[0], B[1], B[2], B[3]}; + m_reg = (__vector unsigned int){B[0], B[1], B[2], B[3]}; } SIMD_Altivec(u32bit B0, u32bit B1, u32bit B2, u32bit B3) { - reg = (__vector unsigned int){B0, B1, B2, B3}; + m_reg = (__vector unsigned int){B0, B1, B2, B3}; } SIMD_Altivec(u32bit B) { - reg = (__vector unsigned int){B, B, B, B}; + m_reg = (__vector unsigned int){B, B, B, B}; } static SIMD_Altivec load_le(const void* in) @@ -80,7 +80,7 @@ class SIMD_Altivec u32bit R[4]; } vec; - vec.V = vec_perm(reg, reg, perm); + vec.V = vec_perm(m_reg, m_reg, perm); Botan::store_be(out, vec.R[0], vec.R[1], vec.R[2], vec.R[3]); } @@ -92,17 +92,15 @@ class SIMD_Altivec u32bit R[4]; } vec; - vec.V = reg; + vec.V = m_reg; Botan::store_be(out, vec.R[0], vec.R[1], vec.R[2], vec.R[3]); } void rotate_left(size_t rot) { - __vector unsigned int rot_vec = - (__vector unsigned int){rot, rot, rot, rot}; - - reg = vec_rl(reg, rot_vec); + const unsigned int r = static_cast<unsigned int>(rot); + m_reg = vec_rl(m_reg, (__vector unsigned int){r, r, r, r}); } void rotate_right(size_t rot) @@ -112,74 +110,73 @@ class SIMD_Altivec void operator+=(const SIMD_Altivec& other) { - reg = vec_add(reg, other.reg); + m_reg = vec_add(m_reg, other.m_reg); } SIMD_Altivec operator+(const SIMD_Altivec& other) const { - return vec_add(reg, other.reg); + return vec_add(m_reg, other.m_reg); } void operator-=(const SIMD_Altivec& other) { - reg = vec_sub(reg, other.reg); + m_reg = vec_sub(m_reg, other.m_reg); } SIMD_Altivec operator-(const SIMD_Altivec& other) const { - return vec_sub(reg, other.reg); + return vec_sub(m_reg, other.m_reg); } void operator^=(const SIMD_Altivec& other) { - reg = vec_xor(reg, other.reg); + m_reg = vec_xor(m_reg, other.m_reg); } SIMD_Altivec operator^(const SIMD_Altivec& other) const { - return vec_xor(reg, other.reg); + return vec_xor(m_reg, other.m_reg); } void operator|=(const SIMD_Altivec& other) { - reg = vec_or(reg, other.reg); + m_reg = vec_or(m_reg, other.m_reg); } SIMD_Altivec operator&(const SIMD_Altivec& other) { - return vec_and(reg, other.reg); + return vec_and(m_reg, other.m_reg); } void operator&=(const SIMD_Altivec& other) { - reg = vec_and(reg, other.reg); + m_reg = vec_and(m_reg, other.m_reg); } SIMD_Altivec operator<<(size_t shift) const { - __vector unsigned int shift_vec = - (__vector unsigned int){shift, shift, shift, shift}; - - return vec_sl(reg, shift_vec); + const unsigned int s = static_cast<unsigned int>(shift); + return vec_sl(m_reg, (__vector unsigned int){s, s, s, s}); } SIMD_Altivec operator>>(size_t shift) const { - __vector unsigned int shift_vec = - (__vector unsigned int){shift, shift, shift, shift}; - - return vec_sr(reg, shift_vec); + const unsigned int s = static_cast<unsigned int>(shift); + return vec_sr(m_reg, (__vector unsigned int){s, s, s, s}); } SIMD_Altivec operator~() const { - return vec_nor(reg, reg); + return vec_nor(m_reg, m_reg); } SIMD_Altivec andc(const SIMD_Altivec& other) { - // AltiVec does arg1 & ~arg2 rather than SSE's ~arg1 & arg2 - return vec_andc(other.reg, reg); + /* + AltiVec does arg1 & ~arg2 rather than SSE's ~arg1 & arg2 + so swap the arguments + */ + return vec_andc(other.m_reg, m_reg); } SIMD_Altivec bswap() const @@ -188,27 +185,27 @@ class SIMD_Altivec perm = vec_xor(perm, vec_splat_u8(3)); - return SIMD_Altivec(vec_perm(reg, reg, perm)); + return SIMD_Altivec(vec_perm(m_reg, m_reg, perm)); } static void transpose(SIMD_Altivec& B0, SIMD_Altivec& B1, SIMD_Altivec& B2, SIMD_Altivec& B3) { - __vector unsigned int T0 = vec_mergeh(B0.reg, B2.reg); - __vector unsigned int T1 = vec_mergel(B0.reg, B2.reg); - __vector unsigned int T2 = vec_mergeh(B1.reg, B3.reg); - __vector unsigned int T3 = vec_mergel(B1.reg, B3.reg); + __vector unsigned int T0 = vec_mergeh(B0.m_reg, B2.m_reg); + __vector unsigned int T1 = vec_mergel(B0.m_reg, B2.m_reg); + __vector unsigned int T2 = vec_mergeh(B1.m_reg, B3.m_reg); + __vector unsigned int T3 = vec_mergel(B1.m_reg, B3.m_reg); - B0.reg = vec_mergeh(T0, T2); - B1.reg = vec_mergel(T0, T2); - B2.reg = vec_mergeh(T1, T3); - B3.reg = vec_mergel(T1, T3); + B0.m_reg = vec_mergeh(T0, T2); + B1.m_reg = vec_mergel(T0, T2); + B2.m_reg = vec_mergeh(T1, T3); + B3.m_reg = vec_mergel(T1, T3); } private: - SIMD_Altivec(__vector unsigned int input) { reg = input; } + SIMD_Altivec(__vector unsigned int input) { m_reg = input; } - __vector unsigned int reg; + __vector unsigned int m_reg; }; } diff --git a/src/lib/utils/cpuid.cpp b/src/lib/utils/cpuid.cpp index c49eb0752..18ef4b959 100644 --- a/src/lib/utils/cpuid.cpp +++ b/src/lib/utils/cpuid.cpp @@ -124,6 +124,7 @@ bool altivec_check_pvr_emul() const u16bit PVR_G5_970GX = 0x0045; const u16bit PVR_POWER6 = 0x003E; const u16bit PVR_POWER7 = 0x003F; + const u16bit PVR_POWER8 = 0x004B; const u16bit PVR_CELL_PPU = 0x0070; // Motorola produced G4s with PVR 0x800[0123C] (at least) @@ -144,6 +145,7 @@ bool altivec_check_pvr_emul() altivec_capable |= (pvr == PVR_G5_970GX); altivec_capable |= (pvr == PVR_POWER6); altivec_capable |= (pvr == PVR_POWER7); + altivec_capable |= (pvr == PVR_POWER8); altivec_capable |= (pvr == PVR_CELL_PPU); #endif |