diff options
| -rw-r--r-- | doc/examples/cpuid.cpp | 5 | ||||
| -rw-r--r-- | src/engine/aes_isa_eng/aes_isa_engine.cpp | 4 | ||||
| -rw-r--r-- | src/utils/cpuid.h | 13 |
3 files changed, 17 insertions, 5 deletions
diff --git a/doc/examples/cpuid.cpp b/doc/examples/cpuid.cpp index 30ac4d676..bc33ef907 100644 --- a/doc/examples/cpuid.cpp +++ b/doc/examples/cpuid.cpp @@ -7,12 +7,15 @@ using namespace Botan; int main() { printf("Cache line size: %d\n", CPUID::cache_line_size()); + printf("RDTSC: %d\n", CPUID::has_rdtsc()); printf("SSE2 %d\n", CPUID::has_sse2()); printf("SSSE3 %d\n", CPUID::has_ssse3()); printf("SSE41 %d\n", CPUID::has_sse41()); printf("SSE42 %d\n", CPUID::has_sse42()); - printf("AES-NI %d\n", CPUID::has_intel_aes()); + printf("AES-NI %d\n", CPUID::has_aes_intel()); + + printf("AES-VIA %d\n", CPUID::has_aes_via()); printf("AltiVec %d\n", CPUID::has_altivec()); } diff --git a/src/engine/aes_isa_eng/aes_isa_engine.cpp b/src/engine/aes_isa_eng/aes_isa_engine.cpp index fd36feb2f..bbbdd288e 100644 --- a/src/engine/aes_isa_eng/aes_isa_engine.cpp +++ b/src/engine/aes_isa_eng/aes_isa_engine.cpp @@ -23,7 +23,7 @@ AES_ISA_Engine::find_block_cipher(const SCAN_Name& request, Algorithm_Factory&) const { #if defined(BOTAN_HAS_AES_INTEL) - if(CPUID::has_intel_aes()) + if(CPUID::has_aes_intel()) { if(request.algo_name() == "AES-128") return new AES_128_Intel; @@ -37,7 +37,7 @@ AES_ISA_Engine::find_block_cipher(const SCAN_Name& request, #endif #if defined(BOTAN_HAS_AES_VIA) - if(CPUID::has_via_aes()) + if(CPUID::has_aes_via()) { if(request.algo_name() == "AES-128") return new AES_128_VIA; diff --git a/src/utils/cpuid.h b/src/utils/cpuid.h index 8b8021754..455721af9 100644 --- a/src/utils/cpuid.h +++ b/src/utils/cpuid.h @@ -60,11 +60,20 @@ class CPUID { return ((x86_processor_flags() >> CPUID_SSE42_BIT) & 1); } /** - * Check if the processor supports Intel AES instructions + * Check if the processor supports Intel's AES instructions */ - static bool has_intel_aes() + static bool has_aes_intel() { return ((x86_processor_flags() >> CPUID_INTEL_AES_BIT) & 1); } + /** + * Check if the processor supports VIA's AES instructions + * (not implemented) + */ + static bool has_aes_via() { return false; } + + /** + * Check if the processor supports AltiVec/VMX + */ static bool has_altivec(); private: static u64bit x86_processor_flags(); |