Rename CPUID::has_intel_aes to has_aes_intel, and add CPUID::has_aes_via,

which is currently just a stub returning false.

2 files changed, 13 insertions, 4 deletions

diff --git a/src/engine/aes_isa_eng/aes_isa_engine.cpp b/src/engine/aes_isa_eng/aes_isa_engine.cpp
index fd36feb2f..bbbdd288e 100644
--- a/src/engine/aes_isa_eng/aes_isa_engine.cpp
+++ b/src/engine/aes_isa_eng/aes_isa_engine.cpp
@@ -23,7 +23,7 @@ AES_ISA_Engine::find_block_cipher(const SCAN_Name& request,
                                   Algorithm_Factory&) const
    {
 #if defined(BOTAN_HAS_AES_INTEL)
-   if(CPUID::has_intel_aes())
+   if(CPUID::has_aes_intel())
       {
       if(request.algo_name() == "AES-128")
          return new AES_128_Intel;
@@ -37,7 +37,7 @@ AES_ISA_Engine::find_block_cipher(const SCAN_Name& request,
 #endif
 
 #if defined(BOTAN_HAS_AES_VIA)
-   if(CPUID::has_via_aes())
+   if(CPUID::has_aes_via())
       {
       if(request.algo_name() == "AES-128")
          return new AES_128_VIA;
diff --git a/src/utils/cpuid.h b/src/utils/cpuid.h
index 8b8021754..455721af9 100644
--- a/src/utils/cpuid.h
+++ b/src/utils/cpuid.h
@@ -60,11 +60,20 @@ class CPUID
          { return ((x86_processor_flags() >> CPUID_SSE42_BIT) & 1); }
 
       /**
-      * Check if the processor supports Intel AES instructions
+      * Check if the processor supports Intel's AES instructions
       */
-      static bool has_intel_aes()
+      static bool has_aes_intel()
          { return ((x86_processor_flags() >> CPUID_INTEL_AES_BIT) & 1); }
 
+      /**
+      * Check if the processor supports VIA's AES instructions
+      * (not implemented)
+      */
+      static bool has_aes_via() { return false; }
+
+      /**
+      * Check if the processor supports AltiVec/VMX
+      */
       static bool has_altivec();
    private:
       static u64bit x86_processor_flags();