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authorlloyd <[email protected]>2009-09-17 18:17:20 +0000
committerlloyd <[email protected]>2009-09-17 18:17:20 +0000
commit87e25c7e270a52fda8c39296be01918bb6aa75d6 (patch)
tree1d8086ed55110cfb21089fc4c1c7a7f2112f1921 /src
parent63fb872cb36a44a852ec33133de7c242bd44427e (diff)
Fix macro generation + checks in configure.py and bswap.h. Had the effect
of preventing the bswap optimizations from being used. :(
Diffstat (limited to 'src')
-rw-r--r--src/utils/bswap.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/utils/bswap.h b/src/utils/bswap.h
index 08095b319..ec1e81435 100644
--- a/src/utils/bswap.h
+++ b/src/utils/bswap.h
@@ -24,7 +24,7 @@ inline u16bit reverse_bytes(u16bit input)
inline u32bit reverse_bytes(u32bit input)
{
-#if BOTAN_COMPILER_HAS_GCC_INLINE_ASM && \
+#if BOTAN_USE_GCC_INLINE_ASM && \
(defined(BOTAN_TARGET_ARCH_IS_IA32) || defined(BOTAN_TARGET_ARCH_IS_AMD64))
/* GCC-style inline assembly for x86 or x86-64 */
@@ -45,7 +45,7 @@ inline u32bit reverse_bytes(u32bit input)
inline u64bit reverse_bytes(u64bit input)
{
-#if BOTAN_COMPILER_HAS_GCC_INLINE_ASM && defined(BOTAN_TARGET_ARCH_IS_AMD64)
+#if BOTAN_USE_GCC_INLINE_ASM && defined(BOTAN_TARGET_ARCH_IS_AMD64)
asm("bswapq %0" : "=r" (input) : "0" (input));
return input;
#else