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authorlloyd <[email protected]>2006-08-13 16:15:50 +0000
committerlloyd <[email protected]>2006-08-13 16:15:50 +0000
commit68ff8a0ae08c41508ded28c73f0acc67023fe5d0 (patch)
treeee4cc05be189d71e884ecc325f6540a955ccd176
parenta41810bd79090f84337c1c345ac43d900790a5cb (diff)
Use the spare register to load the message word, which will potentially
help hide some of the memory latency.
-rw-r--r--modules/alg_ia32/md5core.S10
1 files changed, 7 insertions, 3 deletions
diff --git a/modules/alg_ia32/md5core.S b/modules/alg_ia32/md5core.S
index 7e019c364..510bb14bf 100644
--- a/modules/alg_ia32/md5core.S
+++ b/modules/alg_ia32/md5core.S
@@ -40,32 +40,36 @@ LOOP_UNTIL(ESI, IMM(16), .LOAD_INPUT)
ASSIGN(EDX, ARRAY4(EBP, 3))
#define T1 ESI
+#define T2 EBP
#define FF(A, B, C, D, MSG, S, MAGIC) \
- ADD(A, ARRAY4(EDI, MSG)) ; \
+ ASSIGN(T2, ARRAY4(EDI, MSG)) ; \
ASSIGN(T1, C) ; \
XOR(T1, D) ; \
AND(T1, B) ; \
XOR(T1, D) ; \
+ ADD(A, T2) ; \
ADD3_IMM(A, T1, MAGIC) ; \
ROTL_IMM(A, S) ; \
ADD(A, B) ;
#define GG(A, B, C, D, MSG, S, MAGIC) \
- ADD(A, ARRAY4(EDI, MSG)) ; \
+ ASSIGN(T2, ARRAY4(EDI, MSG)) ; \
ASSIGN(T1, B) ; \
XOR(T1, C) ; \
AND(T1, D) ; \
XOR(T1, C) ; \
+ ADD(A, T2) ; \
ADD3_IMM(A, T1, MAGIC) ; \
ROTL_IMM(A, S) ; \
ADD(A, B) ;
#define HH(A, B, C, D, MSG, S, MAGIC) \
- ADD(A, ARRAY4(EDI, MSG)) ; \
+ ASSIGN(T2, ARRAY4(EDI, MSG)) ; \
ASSIGN(T1, B) ; \
XOR(T1, C) ; \
XOR(T1, D) ; \
+ ADD(A, T2) ; \
ADD3_IMM(A, T1, MAGIC) ; \
ROTL_IMM(A, S) ; \
ADD(A, B) ;