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authorlloyd <[email protected]>2010-01-12 15:48:09 +0000
committerlloyd <[email protected]>2010-01-12 15:48:09 +0000
commitc55ec7dc7487c26338721d108dff78daf906021e (patch)
tree7baeb4ae3a836bc2bcbd6183991db2e78cca9047
parentd46abca140523d12d780910fa725e76f1593f493 (diff)
Add operator& and non-mutating rotates to SIMD_32
-rw-r--r--src/utils/simd_32/simd_32.h16
-rw-r--r--src/utils/simd_32/simd_altivec.h5
-rw-r--r--src/utils/simd_32/simd_scalar.h8
-rw-r--r--src/utils/simd_32/simd_sse.h5
4 files changed, 34 insertions, 0 deletions
diff --git a/src/utils/simd_32/simd_32.h b/src/utils/simd_32/simd_32.h
index 38ea078d0..4bd983f5e 100644
--- a/src/utils/simd_32/simd_32.h
+++ b/src/utils/simd_32/simd_32.h
@@ -27,4 +27,20 @@
#endif
+namespace Botan {
+
+inline SIMD_32 rotate_left(SIMD_32 x, u32bit rot)
+ {
+ x.rotate_left(rot);
+ return x;
+ }
+
+inline SIMD_32 rotate_right(SIMD_32 x, u32bit rot)
+ {
+ x.rotate_right(rot);
+ return x;
+ }
+
+}
+
#endif
diff --git a/src/utils/simd_32/simd_altivec.h b/src/utils/simd_32/simd_altivec.h
index 9cc5c1068..859a48a5f 100644
--- a/src/utils/simd_32/simd_altivec.h
+++ b/src/utils/simd_32/simd_altivec.h
@@ -145,6 +145,11 @@ class SIMD_Altivec
reg = vec_or(reg, other.reg);
}
+ SIMD_Altivec operator&(const SIMD_Altivec& other)
+ {
+ return vec_and(reg, other.reg);
+ }
+
void operator&=(const SIMD_Altivec& other)
{
reg = vec_and(reg, other.reg);
diff --git a/src/utils/simd_32/simd_scalar.h b/src/utils/simd_32/simd_scalar.h
index 148b76c35..5cf1a11c3 100644
--- a/src/utils/simd_32/simd_scalar.h
+++ b/src/utils/simd_32/simd_scalar.h
@@ -142,6 +142,14 @@ class SIMD_Scalar
R3 |= other.R3;
}
+ SIMD_Scalar operator&(const SIMD_Scalar& other)
+ {
+ return SIMD_Scalar(R0 & other.R0,
+ R1 & other.R1,
+ R2 & other.R2,
+ R3 & other.R3);
+ }
+
void operator&=(const SIMD_Scalar& other)
{
R0 &= other.R0;
diff --git a/src/utils/simd_32/simd_sse.h b/src/utils/simd_32/simd_sse.h
index 31bbce2c7..0189c2e4d 100644
--- a/src/utils/simd_32/simd_sse.h
+++ b/src/utils/simd_32/simd_sse.h
@@ -101,6 +101,11 @@ class SIMD_SSE2
reg = _mm_or_si128(reg, other.reg);
}
+ SIMD_SSE2 operator&(const SIMD_SSE2& other)
+ {
+ return _mm_and_si128(reg, other.reg);
+ }
+
void operator&=(const SIMD_SSE2& other)
{
reg = _mm_and_si128(reg, other.reg);