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authorlloyd <[email protected]>2010-06-28 16:05:24 +0000
committerlloyd <[email protected]>2010-06-28 16:05:24 +0000
commit78465d7229c14478b81ecf56fad69a3b598a7415 (patch)
treebd65944bb41cb0d9d9c9961e570f54e24a7728d4
parentcc2e1675e363d1792b6470cd30b2b68e43120120 (diff)
Simplify feature checks
-rw-r--r--src/utils/cpuid.h19
1 files changed, 12 insertions, 7 deletions
diff --git a/src/utils/cpuid.h b/src/utils/cpuid.h
index e0ccee515..a6a278a6e 100644
--- a/src/utils/cpuid.h
+++ b/src/utils/cpuid.h
@@ -27,49 +27,54 @@ class BOTAN_DLL CPUID
* Check if the processor supports RDTSC
*/
static bool has_rdtsc()
- { return ((x86_processor_flags() >> CPUID_RDTSC_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_RDTSC_BIT); }
/**
* Check if the processor supports SSE2
*/
static bool has_sse2()
- { return ((x86_processor_flags() >> CPUID_SSE2_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_SSE2_BIT); }
/**
* Check if the processor supports SSSE3
*/
static bool has_ssse3()
- { return ((x86_processor_flags() >> CPUID_SSSE3_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_SSSE3_BIT); }
/**
* Check if the processor supports SSE4.1
*/
static bool has_sse41()
- { return ((x86_processor_flags() >> CPUID_SSE41_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_SSE41_BIT); }
/**
* Check if the processor supports SSE4.2
*/
static bool has_sse42()
- { return ((x86_processor_flags() >> CPUID_SSE42_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_SSE42_BIT); }
/**
* Check if the processor supports extended AVX vector instructions
*/
static bool has_avx()
- { return ((x86_processor_flags() >> CPUID_AVX_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_AVX_BIT); }
/**
* Check if the processor supports Intel's AES instructions
*/
static bool has_aes_intel()
- { return ((x86_processor_flags() >> CPUID_INTEL_AES_BIT) & 1); }
+ { return x86_processor_flags_has(CPUID_INTEL_AES_BIT); }
/**
* Check if the processor supports AltiVec/VMX
*/
static bool has_altivec();
private:
+ static bool x86_processor_flags_has(u64bit bit)
+ {
+ return ((x86_processor_flags() >> bit) & 1);
+ }
+
enum CPUID_bits {
CPUID_RDTSC_BIT = 4,
CPUID_SSE2_BIT = 26,