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authorRodeo <[email protected]>2015-02-03 13:35:30 +0000
committerRodeo <[email protected]>2015-02-03 13:35:30 +0000
commit24cc4de85ca8bb8d0499d6008947a0045e564210 (patch)
tree1cd5ebec36c0ea650655bb97cd0cae48b811da91 /libhb
parented749ed715a9ea7a83bd45bddc1175cf085b0a99 (diff)
libhb: add support for detection of new Intel processor releases.
git-svn-id: svn://svn.handbrake.fr/HandBrake/trunk@6864 b64f7644-9d1e-0410-96f1-a4d463321fa5
Diffstat (limited to 'libhb')
-rw-r--r--libhb/ports.c15
-rw-r--r--libhb/ports.h2
-rw-r--r--libhb/qsv_common.c6
3 files changed, 22 insertions, 1 deletions
diff --git a/libhb/ports.c b/libhb/ports.c
index f03064a66..4e542b202 100644
--- a/libhb/ports.c
+++ b/libhb/ports.c
@@ -262,6 +262,10 @@ const char* hb_get_cpu_platform_name()
return "Intel microarchitecture Silvermont";
case HB_CPU_PLATFORM_INTEL_HSW:
return "Intel microarchitecture Haswell";
+ case HB_CPU_PLATFORM_INTEL_BDW:
+ return "Intel microarchitecture Broadwell";
+ case HB_CPU_PLATFORM_INTEL_CHT:
+ return "Intel microarchitecture Airmont";
default:
return NULL;
@@ -327,13 +331,24 @@ static void init_cpu_info()
case 0x37:
case 0x4A:
case 0x4D:
+ case 0x5A:
+ case 0x5D:
hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SLM;
break;
case 0x3C:
+ case 0x3F:
case 0x45:
case 0x46:
hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_HSW;
break;
+ case 0x3D:
+ case 0x4F:
+ case 0x56:
+ hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_BDW;
+ break;
+ case 0x4C:
+ hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_CHT;
+ break;
default:
break;
}
diff --git a/libhb/ports.h b/libhb/ports.h
index 2c5dbe6fc..5c9cf9bda 100644
--- a/libhb/ports.h
+++ b/libhb/ports.h
@@ -39,6 +39,8 @@ enum hb_cpu_platform
HB_CPU_PLATFORM_INTEL_IVB,
HB_CPU_PLATFORM_INTEL_SLM,
HB_CPU_PLATFORM_INTEL_HSW,
+ HB_CPU_PLATFORM_INTEL_BDW,
+ HB_CPU_PLATFORM_INTEL_CHT,
};
int hb_get_cpu_count();
int hb_get_cpu_platform();
diff --git a/libhb/qsv_common.c b/libhb/qsv_common.c
index b1a4b26c9..6aa9e805f 100644
--- a/libhb/qsv_common.c
+++ b/libhb/qsv_common.c
@@ -47,6 +47,7 @@ enum
QSV_G1, // Sandy Bridge or equivalent
QSV_G2, // Ivy Bridge or equivalent
QSV_G3, // Haswell or equivalent
+ QSV_G4, // Broadwell or equivalent
};
static int qsv_hardware_generation(int cpu_platform)
{
@@ -58,10 +59,13 @@ static int qsv_hardware_generation(int cpu_platform)
return QSV_G1;
case HB_CPU_PLATFORM_INTEL_IVB:
case HB_CPU_PLATFORM_INTEL_SLM:
+ case HB_CPU_PLATFORM_INTEL_CHT:
return QSV_G2;
case HB_CPU_PLATFORM_INTEL_HSW:
- default:
return QSV_G3;
+ case HB_CPU_PLATFORM_INTEL_BDW:
+ default:
+ return QSV_G4;
}
}