diff options
author | Max Dmytrychenko <[email protected]> | 2015-09-22 20:20:19 +0200 |
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committer | Max Dmytrychenko <[email protected]> | 2015-09-22 20:20:19 +0200 |
commit | ae593691f668fd20cbaafedd263d43b5ead96cb7 (patch) | |
tree | e26fdf4812cef4f5b5eb682ad61463220797a404 /libhb | |
parent | 1be374b5dc275a6e66b1d660ed093234582afa63 (diff) |
libhb: Skylake microarchitecture detection, RB 859
Diffstat (limited to 'libhb')
-rw-r--r-- | libhb/ports.c | 6 | ||||
-rw-r--r-- | libhb/ports.h | 1 | ||||
-rw-r--r-- | libhb/qsv_common.c | 7 |
3 files changed, 13 insertions, 1 deletions
diff --git a/libhb/ports.c b/libhb/ports.c index e93fdb100..23be576b9 100644 --- a/libhb/ports.c +++ b/libhb/ports.c @@ -269,6 +269,8 @@ const char* hb_get_cpu_platform_name() return "Intel microarchitecture Haswell"; case HB_CPU_PLATFORM_INTEL_BDW: return "Intel microarchitecture Broadwell"; + case HB_CPU_PLATFORM_INTEL_SKL: + return "Intel microarchitecture Skylake"; case HB_CPU_PLATFORM_INTEL_CHT: return "Intel microarchitecture Airmont"; @@ -354,6 +356,10 @@ static void init_cpu_info() case 0x4C: hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_CHT; break; + case 0x4E: + case 0x5E: + hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SKL; + break; default: break; } diff --git a/libhb/ports.h b/libhb/ports.h index 5e039809e..d16493043 100644 --- a/libhb/ports.h +++ b/libhb/ports.h @@ -39,6 +39,7 @@ enum hb_cpu_platform HB_CPU_PLATFORM_INTEL_HSW, HB_CPU_PLATFORM_INTEL_BDW, HB_CPU_PLATFORM_INTEL_CHT, + HB_CPU_PLATFORM_INTEL_SKL, }; int hb_get_cpu_count(); int hb_get_cpu_platform(); diff --git a/libhb/qsv_common.c b/libhb/qsv_common.c index 60d371f82..12f4d5e7b 100644 --- a/libhb/qsv_common.c +++ b/libhb/qsv_common.c @@ -108,6 +108,8 @@ enum QSV_G2, // Ivy Bridge or equivalent QSV_G3, // Haswell or equivalent QSV_G4, // Broadwell or equivalent + QSV_G5, // Skylake or equivalent + QSV_FU, // always last (future processors) }; static int qsv_hardware_generation(int cpu_platform) { @@ -124,8 +126,11 @@ static int qsv_hardware_generation(int cpu_platform) case HB_CPU_PLATFORM_INTEL_HSW: return QSV_G3; case HB_CPU_PLATFORM_INTEL_BDW: - default: return QSV_G4; + case HB_CPU_PLATFORM_INTEL_SKL: + return QSV_G5; + default: + return QSV_FU; } } |