diff options
| author | Rodeo <[email protected]> | 2013-12-27 20:49:39 +0000 |
|---|---|---|
| committer | Rodeo <[email protected]> | 2013-12-27 20:49:39 +0000 |
| commit | e087032ff8edb0441eafc225ae860503ce12f3d4 (patch) | |
| tree | cf550b8e074d46aff5a235daf6c8c825660b21ca /libhb/ports.c | |
| parent | 840cb1e3448867a3d56bafc980dce39189d4814f (diff) | |
ports: detect more Intel microarchitecture families.
Also disable QSV hardware support on Bonnell-based microprocessors. Some Cloverview processors apparently support media SDK with third-party hardware, and until we can access hardware to test and fix the crashes we have on that platform, let's not enable it.
git-svn-id: svn://svn.handbrake.fr/HandBrake/trunk@5942 b64f7644-9d1e-0410-96f1-a4d463321fa5
Diffstat (limited to 'libhb/ports.c')
| -rw-r--r-- | libhb/ports.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/libhb/ports.c b/libhb/ports.c index e5c9fe7e2..5b69f16d1 100644 --- a/libhb/ports.c +++ b/libhb/ports.c @@ -247,10 +247,14 @@ const char* hb_get_cpu_platform_name() { // Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3C // Table 35-1: CPUID Signature Values of DisplayFamily_DisplayModel + case HB_CPU_PLATFORM_INTEL_BNL: + return "Intel microarchitecture Bonnell"; case HB_CPU_PLATFORM_INTEL_SNB: return "Intel microarchitecture Sandy Bridge"; case HB_CPU_PLATFORM_INTEL_IVB: return "Intel microarchitecture Ivy Bridge"; + case HB_CPU_PLATFORM_INTEL_SLM: + return "Intel microarchitecture Silvermont"; case HB_CPU_PLATFORM_INTEL_HSW: return "Intel microarchitecture Haswell"; @@ -281,6 +285,13 @@ static void init_cpu_info() { switch (model) { + case 0x1C: + case 0x26: + case 0x27: + case 0x35: + case 0x36: + hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_BNL; + break; case 0x2A: case 0x2D: hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SNB; @@ -289,6 +300,11 @@ static void init_cpu_info() case 0x3E: hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_IVB; break; + case 0x37: + case 0x4A: + case 0x4D: + hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SLM; + break; case 0x3C: case 0x45: case 0x46: |